SLVSE03B April 2019 – February 2021 TPS929120-Q1
PRODUCTION DATA
The internal ADC of TPS92910-Q1 continuously monitors supply voltage and compares the results with internal threshold V(ADCLOWSUPTH) set by CONF_ADCLOWSUPTH as described in Register Maps. If the supply voltage is lower than threshold, the device sets flag registers including FLAG_ADCLOWSUP and FLAG_ERR to 1. Master controller can write register CLR_FAULT to 1 to reset this flag, and the CLR_FAULT bit automatically returns to 0. The internal ADC monitors supply voltage and converters to 8-bit binary code in every conversion cycle T(CONV) when it is in idle.
After each AD conversion cycle time on supply, the ADC_SUPPLY is automatically updated with the latest result.