SLVSEG1A July   2018  – September 2019 TPS56637

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency vs Output Current VOUT = 5 V
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  The Adaptive On-Time Control and PWM Operation
      2. 7.3.2  Mode Selection
        1. 7.3.2.1 Eco-mode™ Control Scheme
        2. 7.3.2.2 FCCM Control
      3. 7.3.3  Soft Start and Pre-Biased Soft Start
      4. 7.3.4  Enable and Adjusting Undervoltage Lockout
      5. 7.3.5  Output Overcurrent Limit and Undervoltage Protection
      6. 7.3.6  Overvoltage Protection
      7. 7.3.7  UVLO Protection
      8. 7.3.8  Thermal Shutdown
      9. 7.3.9  Output Voltage Discharge
      10. 7.3.10 Power Good
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby Operation
      2. 7.4.2 Normal Operation
      3. 7.4.3 Light Load Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Resistors Selection
        2. 8.2.2.2 Output Filter Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Bootstrap Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

8.2.2.2 Output Filter Selection

The LC filter used as the output filter has double pole at:

Equation 6. TPS56637 equation-5-slvseg1.gif

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the device. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP3 introduces a high frequency zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the zero frequency. The inductor and capacitor for the output filter must be selected so that the double pole of Equation 6 is located below the high frequency zero but close enough that the phase boost provided be the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 4.

Table 4. Recommended Component Values

OUTPUT VOLTAGE(1)
(V)		 R6(2)
(kΩ)		 R7
(kΩ)		 L1 (µH) COUT(3)
(µF)		 C9 (pF)(4) R8 (kΩ)(4)
MIN TYP MAX
1.05 7.5 10.0 1 30 35 100
1.2 10 10.0 1 30 35 100
1.8 20 10.0 1.2 30 35 100
3.3 45.3 10.0 2.2 20 35 100 100 to 220 20
5 73.2 10.0 3.3 20 30 100 100 to 220 20
12 191 10.0 5.6 25 30 100 100 to 220 20
(1) Please use the recommended L1 and COUT combination of the higher and closest output rail for unlisted output rails.
(2) R6=0Ω for VOUT=0.6V
(3) COUT is the sum of effective output capacitance. In this datasheet the effective capacitance is defined as the actual capacitance under DC bias and temperature, not the rated or nameplate values. All high value ceramic capacitors have a large voltage coefficient in addition to normal tolerances and temperature effects. A careful study of bias and temperature variation of any capacitor bank should be made in order to ensure that the minimum value of effective capacitance is provided. Refer to the information of DC bias and temperature characteristics from manufacturers of ceramic capacitors.
(4) R8 and C9 can be used to improve the load transient response or improve the loop-phase margin. The application report Optimizing Transient Response of Internally Compensated DCDC Converters with Feed-forward Capacitor is helpful when experimenting with a feed-forward capacitor.

The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 7, Equation 8, and Equation 9. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current.

Use 500 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 8 and the RMS current of Equation 9.

Equation 7. TPS56637 equation-6-slvseg1.gif
Equation 8. TPS56637 equation-7-slvseg1.gif
Equation 9. TPS56637 equation-8-slvseg1.gif

For this design example, the calculated peak current is 7.28A and the calculated RMS current is 6.05 A. The inductor used is IHLP3232DZER3R3M11 with a peak current rating of 10.5A and an RMS current rating of 9.7A.

The capacitor value and ESR determines the amount of output voltage ripple. TheTPS56637 is intended for use with ceramic or other low ESR capacitors. Recommended values range from 20 µF to 100 µF. Use Equation 10 to determine the required RMS current rating for the output capacitor.

Equation 10. TPS56637 equation-9-slvseg1.gif

For this design two MuRata GRM32ER71E226KE15L 22-µF output capacitors are used so that the effective capacitance is 31.08 µF at DC biased voltage of 5V. The calculated RMS current is 0.738A and each output capacitor is rated for 4 A.