SLVSEN9F April   2019  – June 2024 ADC12DJ5200RF

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 5.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Comparison
      2. 6.3.2  Analog Inputs
        1. 6.3.2.1 Analog Input Protection
        2. 6.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.2.3 Analog Input Offset Adjust
      3. 6.3.3  ADC Core
        1. 6.3.3.1 ADC Theory of Operation
        2. 6.3.3.2 ADC Core Calibration
        3. 6.3.3.3 Analog Reference Voltage
        4. 6.3.3.4 ADC Overrange Detection
        5. 6.3.3.5 Code Error Rate (CER)
      4. 6.3.4  Temperature Monitoring Diode
      5. 6.3.5  Timestamp
      6. 6.3.6  Clocking
        1. 6.3.6.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 6.3.6.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 6.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 6.3.6.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 6.3.6.3.2 Automatic SYSREF Calibration
      7. 6.3.7  Programmable FIR Filter (PFIR)
        1. 6.3.7.1 Dual Channel Equalization
        2. 6.3.7.2 Single Channel Equalization
        3. 6.3.7.3 Time Varying Filter
      8. 6.3.8  Digital Down Converters (DDC)
        1. 6.3.8.1 Rounding and Saturation
        2. 6.3.8.2 Numerically-Controlled Oscillator and Complex Mixer
          1. 6.3.8.2.1 NCO Fast Frequency Hopping (FFH)
          2. 6.3.8.2.2 NCO Selection
          3. 6.3.8.2.3 Basic NCO Frequency Setting Mode
          4. 6.3.8.2.4 Rational NCO Frequency Setting Mode
          5. 6.3.8.2.5 NCO Phase Offset Setting
          6. 6.3.8.2.6 NCO Phase Synchronization
        3. 6.3.8.3 Decimation Filters
        4. 6.3.8.4 Output Data Format
        5. 6.3.8.5 Decimation Settings
          1. 6.3.8.5.1 Decimation Factor
          2. 6.3.8.5.2 DDC Gain Boost
      9. 6.3.9  JESD204C Interface
        1. 6.3.9.1 Transport Layer
        2. 6.3.9.2 Scrambler
        3. 6.3.9.3 Link Layer
        4. 6.3.9.4 8B/10B Link Layer
          1. 6.3.9.4.1 Data Encoding (8B/10B)
          2. 6.3.9.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 6.3.9.4.3 Code Group Synchronization (CGS)
          4. 6.3.9.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 6.3.9.4.5 Frame and Multiframe Monitoring
        5. 6.3.9.5 64B/66B Link Layer
          1. 6.3.9.5.1 64B/66B Encoding
          2. 6.3.9.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
          3. 6.3.9.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
            1. 6.3.9.5.3.1 Cyclic Redundancy Check (CRC) Mode
            2. 6.3.9.5.3.2 Forward Error Correction (FEC) Mode
          4. 6.3.9.5.4 Initial Lane Alignment
          5. 6.3.9.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 6.3.9.6 Physical Layer
          1. 6.3.9.6.1 SerDes Pre-Emphasis
        7. 6.3.9.7 JESD204C Enable
        8. 6.3.9.8 Multi-Device Synchronization and Deterministic Latency
        9. 6.3.9.9 Operation in Subclass 0 Systems
      10. 6.3.10 Alarm Monitoring
        1. 6.3.10.1 Clock Upset Detection
        2. 6.3.10.2 FIFO Upset Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Dual-Channel Mode
      2. 6.4.2 Single-Channel Mode (DES Mode)
      3. 6.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)
      4. 6.4.4 JESD204C Modes
        1. 6.4.4.1 JESD204C Operating Modes Table
        2. 6.4.4.2 JESD204C Modes continued
        3. 6.4.4.3 JESD204C Transport Layer Data Formats
        4. 6.4.4.4 64B/66B Sync Header Stream Configuration
        5. 6.4.4.5 Dual DDC and Redundant Data Mode
      5. 6.4.5 Power-Down Modes
      6. 6.4.6 Test Modes
        1. 6.4.6.1 Serializer Test-Mode Details
        2. 6.4.6.2 PRBS Test Modes
        3. 6.4.6.3 Clock Pattern Mode
        4. 6.4.6.4 Ramp Test Mode
        5. 6.4.6.5 Short and Long Transport Test Mode
          1. 6.4.6.5.1 Short Transport Test Pattern
        6. 6.4.6.6 D21.5 Test Mode
        7. 6.4.6.7 K28.5 Test Mode
        8. 6.4.6.8 Repeated ILA Test Mode
        9. 6.4.6.9 Modified RPAT Test Mode
      7. 6.4.7 Calibration Modes and Trimming
        1. 6.4.7.1 Foreground Calibration Mode
        2. 6.4.7.2 Background Calibration Mode
        3. 6.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 6.4.8 Offset Calibration
      9. 6.4.9 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
        1. 6.5.1.1 SCS
        2. 6.5.1.2 SCLK
        3. 6.5.1.3 SDI
        4. 6.5.1.4 SDO
        5. 6.5.1.5 Streaming Mode
    6. 6.6 SPI Register Map
  8. 7 Application Information Disclaimer
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Wideband RF Sampling Receiver
        1. 7.2.1.1 Design Requirements
          1. 7.2.1.1.1 Input Signal Path
          2. 7.2.1.1.2 Clocking
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Calculating Values of AC-Coupling Capacitors
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Reconfigurable Dual-Channel 5-GSPS or Single-Channel 10-Gsps Oscilloscope
        1. 7.2.2.1 Design Requirements
          1. 7.2.2.1.1 Input Signal Path
          2. 7.2.2.1.2 Clocking
          3. 7.2.2.1.3 ADC12DJ5200RF Ososcilloscope Applications
        2. 7.2.2.2 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.10 Switching Characteristics

typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 5.12 GHz, filtered 1-VPP sine-wave clock, JMODE = 1, Dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DEVICE (SAMPLING) CLOCK (CLK+, CLK–)
tAD Sampling (aperture) delay from the CLK± rising edge (dual-channel mode) or rising and falling edge (single-channel mode) to sampling instant TAD_COARSE = 0x00, TAD_FINE = 0x00, and TAD_INV = 0 360 ps
tTAD(MAX) Maximum tAD adjust programmable delay, not including clock inversion (TAD_INV = 0) Coarse adjustment (TAD_COARSE = 0xFF) 289 ps
Fine adjustment (TAD_FINE = 0xFF) 4.9 ps
tTAD(STEP) tAD adjust programmable delay step size Coarse adjustment (TAD_COARSE) 1.13 ps
Fine adjustment (TAD_FINE) 19 fs
tAJ Aperture jitter, rms Minimum tAD adjust coarse setting (TAD_COARSE = 0x00, TAD_INV = 0), dither disabled (ADC_DITH_EN = 0) 50 fs
Minimum tAD adjust coarse setting (TAD_COARSE = 0x00, TAD_INV = 0), dither enabled (ADC_DITH_EN = 1) 60 fs
Maximum tAD adjust coarse setting (TAD_COARSE = 0xFF) excluding TAD_INV (TAD_INV = 0), dither disabled (ADC_DITH_EN = 0) 65(3)
Maximum tAD adjust coarse setting (TAD_COARSE = 0xFF) excluding TAD_INV (TAD_INV = 0), dither enabled (ADC_DITH_EN = 1) 74(3)
SERIAL DATA OUTPUTS (DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)
fSERDES Serialized output bit rate 1 17.16 Gbps
UI Serialized output unit interval 58.2 1000 ps
tTLH Low-to-high transition time (differential) 20% to 80%, 8H8L test pattern, 17.16 Gbps 18.9 ps
tTHL High-to-low transition time (differential) 20% to 80%, 8H8L test pattern, 17.16 Gbps 18.8 ps
DDJ Data dependent jitter, peak-to-peak PRBS-7 test pattern, JMODE = 19, 12.8 Gbps 9.0 ps
PRBS-9 test pattern, JMODE = 30, 17.16 Gbps 10.0
DCD Even-odd jitter, peak-to-peak PRBS-7 test pattern, JMODE = 19, 12.8 Gbps .33 ps
PRBS-9 test pattern, JMODE = 30, 17.16 Gbps .6
EBUJ Effective bounded uncorrelated jitter, peak-to-peak PRBS-7 test pattern, JMODE = 19, 12.8 Gbps 1.7 ps
PRBS-9 test pattern, JMODE = 30, 17.16 Gbps 1.93
RJ Unbounded random jitter, RMS 8H8L test pattern, JMODE = 19, 12.8 Gbps 0.85 ps
PRBS-9 test pattern, JMODE = 30, 17.16 Gbps 0.88
TJ Total jitter, peak-to-peak, with unbounded random jitter portion defined with respect to a BER = 1e-15 (Q = 7.94) PRBS-7 test pattern, JMODE = 19, 12.8 Gbps 23.3 ps
PRBS-9 test pattern, JMODE = 30, 17.16 Gbps 22.6
ADC CORE LATENCY
tADC Deterministic delay from the CLK± edge that samples the reference sample to the CLK± edge that samples SYSREF going high(1) JMODE = 0, 30, 32 2.5 tCLK cycles
JMODE = 1, 5, 19, 40, 42, 44 -9.5
JMODE = 2, 31, 33 2
JMODE = 3, 7, 20 -10
JMODE = 6, 50 -13.5
JMODE = 8, 51 -14
JMODE = 10, 37 183
JMODE = 11, 47 171
JMODE = 12, 53 167
JMODE = 13, 39 372
JMODE = 14, 15, 49, 55 364
JMODE = 16 356
JMODE = 21, 36 148
JMODE = 22, 46 142
JMODE = 23, 38 223.5
JMODE = 24, 48 219.5
JMODE = 25, 52 138
JMODE = 26, 54 211.5
JMODE = 27 207.5
JMODE = 34 6.5
JMODE = 35 6
JMODE = 41, 43, 45 -10.0
JMODE = 56, 59 750
JMODE = 57, 58, 60 742
JMODE = 61, 62, 63, 64, 65 403.5
JMODE = 66, 67, 68 1514
JMODE = 69, 70, 71 777.5
JESD204C AND SERIALIZER LATENCY
tTX Delay from the CLK± rising edge that samples SYSREF high to the first bit of the multiframe (8B/10B encoding) or extended multiblock (64B/66B encoding) on the JESD204C serial output lane corresponding to the reference sample of tADC(2) JMODE = 0 92 111 tCLK cycles
JMODE = 1 159 182
JMODE = 2 93 111
JMODE = 3 159 188
JMODE = 5 143 168
JMODE = 6, 8, 12, 15, 25, 26 191 215
JMODE = 7, 11, 22 143 168
JMODE = 10 85 103
JMODE = 13, 21, 23 85 102
JMODE = 14, 24 143 166
JMODE = 16, 27 280 305
JMODE = 19, 20 143 165
JMODE = 30, 31 114 134
JMODE = 32, 34, 36 102 119
JMODE = 33, 35, 37 103 119
JMODE = 38 102 118
JMODE = 39 103 118
JMODE = 40 205 229
JMODE = 41 206 229
JMODE = 42, 43, 48, 49 179 200
JMODE = 44, 45, 46, 47 179 202
JMODE = 50, 52, 54 267 291
JMODE = 51, 53, 55 268 291
JMODE = 56, 61 143 165
JMODE = 57, 62 191 213
JMODE = 58, 63 280 305
JMODE = 59, 64 179 199
JMODE = 60 268 289
JMODE = 65 267 289
JMODE = 66, 69 191 212
JMODE = 67, 70 280 304
JMODE = 68 268 288
JMODE = 71 267 288
SERIAL PROGRAMMING INTERFACE (SDO)
t(OZD) Delay from the falling edge of the 16th SCLK cycle during read operation for SDO transition from tri-state to valid data 1 ns
t(ODZ) Delay from the SCS rising edge for SDO transition from valid data to tri-state 10 ns
t(OD) Delay from the falling edge of SCLK during read operation to SDO valid 1 12 ns
(1) tADC is an exact, unrounded, deterministic delay. The delay can be negative if the reference sample is sampled after the SYSREF high capture point, in which case the total latency is smaller than the delay given by tTX.
(2) The values given for tTX include deterministic and non-deterministic delays. Over process, temperature, and voltage, the delay will vary. JESD204B accounts for these variations when operating in subclass-1 mode in order to achieve deterministic latency. Proper receiver RBD values must be chosen such that the elastic buffer release point does not occur within the invalid region of the local multiframe clock (LMFC) cycle.
(3) tAJ increases because of additional attenuation on the internal clock path.