SLVSGZ1A May   2024  – July 2024 DRV8161 , DRV8162

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 1pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gate Drivers
        1. 7.3.1.1 PWM Control Modes
          1. 7.3.1.1.1 2-pin PWM Mode
          2. 7.3.1.1.2 1-pin PWM Mode (preview only)
          3. 7.3.1.1.3 Independent PWM Mode
        2. 7.3.1.2 Gate Drive Architecture
          1. 7.3.1.2.1 Tickle Charge Pump (TCP)
          2. 7.3.1.2.2 Deadtime and Cross-Conduction Prevention (Shoot through protection)
      2. 7.3.2 Pin Diagrams
        1. 7.3.2.1 Four Level Input Pin (CSAGAIN)
        2. 7.3.2.2 Digital output nFAULT (DRV8162, DRV8162L)
        3. 7.3.2.3 Digital InOut nFAULT/nDRVOFF (DRV8161)
        4. 7.3.2.4 Multi-level inputs (IDRIVE1 and IDRIVE2)
        5. 7.3.2.5 Multi-level digital input (VDSLVL)
        6. 7.3.2.6 Multi-level digital input DT/MODE
      3. 7.3.3 Low-Side Current Sense Amplifiers
        1. 7.3.3.1 Bidirectional Current Sense Operation
      4. 7.3.4 Gate Driver Shutdown Sequence (nDRVOFF)
        1. 7.3.4.1 nDRVOFF Diagnostic
      5. 7.3.5 Gate Driver Protective Circuits
        1. 7.3.5.1 GVDD Undervoltage Lockout (GVDD_UV)
        2. 7.3.5.2 MOSFET VDS Overcurrent Protection (VDS_OCP)
        3. 7.3.5.3 Thermal Shutdown (OTSD)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application with DRV8161
      2. 8.2.2 Typical Application with DRV8162 and DRV8162L
      3. 8.2.3 External Components
  10. 9 Layout
    1. 9.1 Layout Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Device Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

3 Description

The DRV816x devices are half-bridge gate drivers capable of driving high-side and low-side N-channel MOSFETs. The gate drive voltages are generated from the GVDD supply pin and the integrated bootstrap circuit is used to drive the high-side FET up to 102V drain. The Smart Gate Drive architecture supports 16-level (48 combination) gate drive peak current up to 1A source and 2A sink, and a built-in timing control of gate drive current. The devices can be used to drive various types of loads including brushless/brushed DC motors, PMSM, stepper motors, SRM, and solenoids.

Internal protection functions are provided for supply undervoltage, FET over-current, and die over temperature. The nFAULT pin indicates fault events detected by the protection features. The nDRVOFF pin initiates power stage shutdown independent from PWM control. The DRV8162 and DRV8162L devices offer split power supply architecture to assist safe torque off (STO) function.

Many device parameters including gate drive current, dead time, PWM control interface, and over current detection are configurable with a few passive components connected to device pins. An integrated low-side current sense amplifier (DRV8161) provides current measurement information back to the controller.

Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
DRV8161 VSSOP (20) 5.1mm × 3.0mm
DRV8162(2) VSSOP (20) 5.1mm × 3.0mm
(1) For more information, see Section 12
(2) Includes DRV8162 (Product Preview) and DRV8162L (Advance Information) device variant. See the Device Comparison Table.
DRV8161 DRV8162 DRV816x Simplified Schematic DRV816x Simplified Schematic