SLVSGZ1A
May 2024 – July 2024
DRV8161
,
DRV8162
ADVANCE INFORMATION
1
1
Features
2
Applications
3
Description
4
Device Comparison Table
5
Pin Configuration and Functions
6
Specification
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information 1pkg
6.5
Electrical Characteristics
6.6
Timing Diagrams
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Gate Drivers
7.3.1.1
PWM Control Modes
7.3.1.1.1
2-pin PWM Mode
7.3.1.1.2
1-pin PWM Mode (preview only)
7.3.1.1.3
Independent PWM Mode
7.3.1.2
Gate Drive Architecture
7.3.1.2.1
Tickle Charge Pump (TCP)
7.3.1.2.2
Deadtime and Cross-Conduction Prevention (Shoot through protection)
7.3.2
Pin Diagrams
7.3.2.1
Four Level Input Pin (CSAGAIN)
7.3.2.2
Digital output nFAULT (DRV8162, DRV8162L)
7.3.2.3
Digital InOut nFAULT/nDRVOFF (DRV8161)
7.3.2.4
Multi-level inputs (IDRIVE1 and IDRIVE2)
7.3.2.5
Multi-level digital input (VDSLVL)
7.3.2.6
Multi-level digital input DT/MODE
7.3.3
Low-Side Current Sense Amplifiers
7.3.3.1
Bidirectional Current Sense Operation
7.3.4
Gate Driver Shutdown Sequence (nDRVOFF)
7.3.4.1
nDRVOFF Diagnostic
7.3.5
Gate Driver Protective Circuits
7.3.5.1
GVDD Undervoltage Lockout (GVDD_UV)
7.3.5.2
MOSFET VDS Overcurrent Protection (VDS_OCP)
7.3.5.3
Thermal Shutdown (OTSD)
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Typical Application with DRV8161
8.2.2
Typical Application with DRV8162 and DRV8162L
8.2.3
External Components
9
Layout
9.1
Layout Guidelines
10
Device and Documentation Support
10.1
Device Support
10.2
Documentation Support
10.2.1
Related Documentation
10.3
Receiving Notification of Documentation Updates
10.4
Community Resources
10.5
Trademarks
11
Revision History
12
Mechanical, Packaging, and Orderable Information
12.1
Tape and Reel Information
7
Detailed Description