SLVSGZ1A May   2024  – July 2024 DRV8161 , DRV8162

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 1pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gate Drivers
        1. 7.3.1.1 PWM Control Modes
          1. 7.3.1.1.1 2-pin PWM Mode
          2. 7.3.1.1.2 1-pin PWM Mode (preview only)
          3. 7.3.1.1.3 Independent PWM Mode
        2. 7.3.1.2 Gate Drive Architecture
          1. 7.3.1.2.1 Tickle Charge Pump (TCP)
          2. 7.3.1.2.2 Deadtime and Cross-Conduction Prevention (Shoot through protection)
      2. 7.3.2 Pin Diagrams
        1. 7.3.2.1 Four Level Input Pin (CSAGAIN)
        2. 7.3.2.2 Digital output nFAULT (DRV8162, DRV8162L)
        3. 7.3.2.3 Digital InOut nFAULT/nDRVOFF (DRV8161)
        4. 7.3.2.4 Multi-level inputs (IDRIVE1 and IDRIVE2)
        5. 7.3.2.5 Multi-level digital input (VDSLVL)
        6. 7.3.2.6 Multi-level digital input DT/MODE
      3. 7.3.3 Low-Side Current Sense Amplifiers
        1. 7.3.3.1 Bidirectional Current Sense Operation
      4. 7.3.4 Gate Driver Shutdown Sequence (nDRVOFF)
        1. 7.3.4.1 nDRVOFF Diagnostic
      5. 7.3.5 Gate Driver Protective Circuits
        1. 7.3.5.1 GVDD Undervoltage Lockout (GVDD_UV)
        2. 7.3.5.2 MOSFET VDS Overcurrent Protection (VDS_OCP)
        3. 7.3.5.3 Thermal Shutdown (OTSD)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application with DRV8161
      2. 8.2.2 Typical Application with DRV8162 and DRV8162L
      3. 8.2.3 External Components
  10. 9 Layout
    1. 9.1 Layout Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Device Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
7.3.1.1.3 Independent PWM Mode

DRV816x supports independent PWM mode, the INH and INL pins control the outputs, GH and GL, respectively. This control mode lets the device drive separate high-side and low-side load. The independent PWM drive mode can be used for various type of loads including solenoids, Switched Reluctance Motor (SRM), unidirectional brushed DC motors, and low-side and high-side switches. In this mode, turning on both the high-side and low-side MOSFETs at the same time in a given half bridge gate driver is possible to use the device as a high-side or low-side driver. The shoot-through protection and dead time are bypassed in the mode.

Table 7-3 Independent PWM Mode Truth Table
INL INH GL GH
0 0 L L
0 1 L H
1 0 H L
1 1 H H

Figure 7-3 shows how the device can be used to connect an inductive load where both the high-side and low-side MOSFETs can be turned on at the same time to drive the load without causing shoot-through. The external diodes for current recirculation are recommended. This configuration helps the design of solenoids or applications. The trickle charge pump is enabled all the time regardless of low-side PWM activity.

Note: The low-side VDS monitor of DRV816x is not available if independent PWM mode is configured. For DRV8161, the CSA output can be monitored by MCU to detect the over current condition.

DRV8161 DRV8162 Independent PWM mode for single load between high-side and low-side Figure 7-3 Independent PWM mode for single load between high-side and low-side

Figure 7-4shows how the device can be used to connect a high-side load and a low-side load at the same time with one half-bridge and drive the loads independently.

DRV8161 DRV8162 Independent PWM mode for high-side and low-side independent loads Figure 7-4 Independent PWM mode for high-side and low-side independent loads