SLVSGZ1A May 2024 – July 2024 DRV8161 , DRV8162
ADVANCE INFORMATION
PIN | TYPE | DESCRIPTION | ||
---|---|---|---|---|
NAME | NO. | |||
DRV8161 20-pin |
DRV8162, DRV8162L 20-pin |
|||
DT/MODE | 1 | 1 | I | Selects input pin interface logic and gate drive dead time setting. Connect a resistor between DT and GND to adjust dead time between 20 ns to 1000 ns, and select a PWM mode. |
INLH/IN | 2 | 2 | I | Gate driver control input. Gate driver control depends on DT/MODE pin setting. |
INL/EN | 3 | 3 | I | Gate driver control input. Gate driver control depends on DT/MODE pin setting. |
NC | — | 4 | N/A | No Connect. Leave open. |
nDRVOFF | — | 5 | I | Gate driver shutdown control. Pulling nDRVOFF low turns off high-side and low-side external MOSFETs by putting the gate drivers into the pull-down state. |
nFAULT/nDRVOFF | 4 | — | I/OD | Shared fault indicator pin and gate driver shutdown pin. Connect this pin to an external pull-up resistor to the controller supply or a controller output pin. This pin is pulled logic low during a fault condition. To active gate drive shutdown, pull the pin low by external logic. |
nFAULT | — | 6 | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pull-up resistor to controller I/O supply, 3.3V to 5.0V. |
VDSLVL | 5 | 7 | I | VDS monitor threshold setting. This pin is a multilevel input pin set by an external resistor. |
CSAREF | 6 | — | PWR | Current sense amplifier reference. Connect a capacitor between the CSAREF and GND pins. |
SO | 7 | — | O | Current sense amplifier output. |
CSAGAIN | 8 | — | I | Gain settings for current sense amplifier. This pin is a multilevel input pin set by an external resistor. |
IDRIVE1 | 9 | 8 | I | Gate drive source and sink current setting. This pin is a multilevel input pin set by an external resistor. |
NC | 9, 16 | No Connect. Leave open. | ||
GVDD | 10 | 10 | PWR | Gate driver power supply input. Connect a capacitor between the GVDD and GND pins. |
IDRIVE2 | 11 | 11 | I | Gate drive source and sink current setting. This pin is a multilevel input pin set by an external resistor. |
GND | 12 | 12 | PWR | Device ground. |
GVDD_LS | — | 13 | PWR | Low-side gate driver power supply input (DRV8162 and DRV8162L only). Connect a capacitor between the GVDD_LS and GND pins. |
SN | 13 | — | I | Current sense amplifier input. Connect to the low-side of the current shunt resistor. |
SP | 14 | — | I | Current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. |
SL | 15 | 14 | I | Low-side source pin. Connect to the low-side power MOSFET source. This pin is an input for the VDS monitor and the output for the low-side gate driver sink. |
GL | 16 | 15 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. |
GH | 17 | 17 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. |
SH | 18 | 18 | I | High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink. |
BST | 19 | 19 | O | Bootstrap output pin. Connect a capacitor between BST and SH. |
VDRAIN | 20 | 20 | PWR | High-side MOSFET drain sense input for VDS monitor and charge pump reference. Connect to the high-side MOSFET drain. |
THERMAL PAD | PWR | Leave open, or tied to GND |
PWR = power, I = input, O = output, NC = no connection, OD = open-drain output