SLVSH13 August   2024 TPSM83102

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Rating
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics 
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout (UVLO)
      2. 7.3.2 Enable and Soft Start
      3. 7.3.3 Adjustable Output Voltage
      4. 7.3.4 Reverse Current Operation
      5. 7.3.5 Protection Features
        1. 7.3.5.1 Input Overvoltage Protection
        2. 7.3.5.2 Short Circuit Protection
        3. 7.3.5.3 Thermal Shutdown
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard-, Fast-, and Fast-Mode Plus Protocol
      3. 7.5.3 I2C Update Sequence
    6. 7.6 Register Map
      1. 7.6.1 Register Description
        1. 7.6.1.1 Register Map
        2. 7.6.1.2 Register CONTROL1 (Register address: 0x02; Default: 0x08)
        3. 7.6.1.3 Register VOUT (Register address: 0x03; Default: 0x5C)
        4. 7.6.1.4 Register CONTROL2 (Register address: 0x05; Default: 0x45)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design with WEBENCH Tools
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Setting the Output Voltage
      3. 8.2.3 Application Curves
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design with WEBENCH Tools
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Mechanical Data

7.6.1.4 Register CONTROL2 (Register address: 0x05; Default: 0x45)

Return to Register Map

Table 7-6 Register CONTROL2 Format
7 6 5 4 3 2 1 0
FPWM FAST_RAMP_EN EN_DISCH_VOUT[1:0] CL_RAMP_MIN TD_RAMP[2:0]
R/W R/W R/W R/W R/W

LEGEND: R/W = Read/Write

Table 7-7 Register CONTROL2 Field Descriptions
Bit Field Type Reset Description
7 FPWM R/W 0b0 Force PWM operation

0 : DISABLE, 1 : ENABLE
6 FAST_RAMP_EN R/W 0b1 Device can start-up faster then VOUT ramp

0 : DISABLE, 1 : ENABLE
5:4 EN_DISCH_VOUT[1:0] R/W 0b00 Enable of BUBO Vout Discharge

00 : DISABLE

01 : SLOW (34mA)

10 : MEDIUM (67mA)

11 : FAST (100mA)
3 CL_RAMP_MIN R/W 0b0 Define the minimum current limit during the soft start ramp

0 : Low (500mA)

1 : High (2x Low)
2:0 TD_RAMP[2:0] R/W 0b101 Defines the ramp time for the Vo soft start ramp

000: 0.256ms

001: 0.512ms

010: 1.024ms

011: 1.920ms

100: 3.584ms

101: 7.552ms

110: 9.600ms

111: 24.320ms