SLVUBD0A January   2018  – July 2021 TPS563240 , TPS563249

 

  1.   Trademarks
  2. 1Introduction
  3. 2Performance Specification Summary
  4. 3Modifications
  5. 4Test Setup
    1. 4.1 Input/Output Connections
    2. 4.2 Start-Up Procedure
  6. 5Board Layout
  7. 6Schematic, Bill of Materials, and Reference
    1. 6.1 Schematic
    2. 6.2 Bill of Materials
  8. 7Revision History

5 Board Layout

This section provides a description of the TPS563249EVM-031, board layout, and layer illustrations.

The board layout for the TPS563249EVM-031 is shown in Figure 5-1, and Figure 5-2. The top layer contains the main power traces for VIN, VOUT, and ground. Also on the top layer are connections for the pins of the TPS563249 and a large area filled with ground. Most of the signal traces are also located on the top side. The input decoupling capacitors, C1, C2, and C3 are located as close to the IC as possible. The input and output connectors, test points, and all of the components are located on the top side. The bottom layer is a ground plane along with the switching node copper fill, signal ground copper fill and the feed back trace from the point of regulation to the top of the resistor divider network.

GUID-74714A63-20E2-40E7-A666-40DED5E0C482-low.pngFigure 5-1 Top Layer
GUID-5BD2B5D0-BCBB-43DD-919A-69F921DDB1EE-low.pngFigure 5-2 Bottom Layer