SLVUBV0A March   2020  – September 2020 TPS55288

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Performance Specification
    2. 1.2 Modification
      1. 1.2.1 Modification
  3. 2Connector, Test Point, and Jumper Descriptions
    1. 2.1 Connector and Test Point Descriptions
    2. 2.2 Jumper Configuration
      1. 2.2.1 JP1 (ENABLE)
      2. 2.2.2 JP2 and JP3 (External Feedback and Internal Feedback Selection)
      3. 2.2.3 JP4 (SYNC)
  4. 3Test Procedure
  5. 4Software User Interface
    1. 4.1 Install USB2ANY Explorer
    2. 4.2 GUI Installation
    3. 4.3 Interface Hardware Setup
    4. 4.4 User Interface Operation
    5. 4.5 Register Map Screen
  6. 5Schematic, Bill of Materials, and Board Layout
    1. 5.1 Schematic
    2. 5.2 Bill of Materials
    3. 5.3 Board Layout
  7.   Revision History

2.2.2 JP2 and JP3 (External Feedback and Internal Feedback Selection)

The JP2 jumper is for the external feedback or the internal feedback selection. By default, this jumper is set to the FB_INT position. Place this jumper in the FB_EXT position for the external output voltage feedback.

The JP3 jumper is for the external feedback connection. Placing a jumper across JP3 when uses external feedback. Left JP3 opens when uses internal feedback.

When using external output voltage feedback, the output voltage is determined by the following equation:

Equation 1. GUID-6827EB5D-3102-47D4-8785-27E3A52B8614-low.gif

It is recommended to use 100 kΩ for the up resistor RFB_UP. The reference voltage VREF at the FB/INT pin is programmable from 45 mV to 1.2 V by writing a 10-bit data into the register 00H and 01H.