SLVUC06 October   2020 TPS650320-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2EVM Configurations
    1. 2.1 Requirements
    2. 2.2 Operation Instructions
    3. 2.3 Configuring the USB to I2C Adapter
    4. 2.4 Regulator Input Supplies and Features
      1. 2.4.1 Buck 1 Input Supply
      2. 2.4.2 Mid-Vin Buck1 Features
      3. 2.4.3 Buck 2 Input Supply
      4. 2.4.4 Buck 3 Input Supply
      5. 2.4.5 Low-Vin Buck2 and Buck3 Features
      6. 2.4.6 Low Noise LDO Input Supply
      7. 2.4.7 Low Noise LDO Features
    5. 2.5 Selecting the Logic Supply Voltage
  4. 3Test Points
    1. 3.1 Voltage Test Points
  5. 4Graphical User Interface
    1. 4.1 TPS650320-Q1 EVM Debugging
      1. 4.1.1 I2C Communication Port and Adapter Debugging
      2. 4.1.2 Updating MCU Firmware
    2. 4.2 Navigating the GUI
      1. 4.2.1 Home
      2. 4.2.2 Block Diagram
      3. 4.2.3 Registers
      4. 4.2.4 Device Configuration
        1. 4.2.4.1 Using Device Configuration to Define Spin Settings
        2. 4.2.4.2 Configuring the Power Sequence
    3. 4.3 Re-Program PMIC
    4. 4.4 In-Circuit Programming
  6. 5Typical Performance Plots
    1. 5.1 Power Sequence Plots
    2. 5.2 Load Transient Plots
    3. 5.3 Output Voltage Ripple Plots
    4. 5.4 Efficiency Plots
    5. 5.5 LDO Output Noise
  7. 6TPS650320-Q1 EVM Schematic
  8. 7TPS650320-Q1 EVM PCB Layers
  9. 8TPS650320-Q1 EVM Bill of Materials

4.2.4.2 Configuring the Power Sequence

The Sequencing Overview tab includes instruments to customize the power sequence of the PMIC. Note that the check boxes are power sequence masks. If a particular logic signal needs to be included as part of the regulator or logic power up sequence, leave the box next to the logic signal unchecked. TI recommends to set Power On Bit unmasked for each rail that is required in the application.

GUID-20200915-CA0I-BRTR-QZLP-1D84XVD20V5L-low.png Figure 4-10 Sequencing Overview Tab
For reference, the GUI can generate example power-up and power-down timing diagrams based on the sequence settings present when the UPDATING TIMING DIAGRAM button is clicked. As noted, rise and fall times are approximate, and the maximum sequence length is 200 ms. Changes to regulator enable and output discharge settings are reflected in the timing diagram. If the sequence settings are not valid, the GUI will provide a notifying message and the timing diagram will not be updated. For example, if a regulator is enabled but fails to power-up within 200 ms, the sequence settings are not valid.
GUID-20200930-CA0I-CPPL-7GW1-D7KV0NNTV2RK-low.png Figure 4-11 GUI Generated Timing Diagram