SLVUC06 October   2020 TPS650320-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2EVM Configurations
    1. 2.1 Requirements
    2. 2.2 Operation Instructions
    3. 2.3 Configuring the USB to I2C Adapter
    4. 2.4 Regulator Input Supplies and Features
      1. 2.4.1 Buck 1 Input Supply
      2. 2.4.2 Mid-Vin Buck1 Features
      3. 2.4.3 Buck 2 Input Supply
      4. 2.4.4 Buck 3 Input Supply
      5. 2.4.5 Low-Vin Buck2 and Buck3 Features
      6. 2.4.6 Low Noise LDO Input Supply
      7. 2.4.7 Low Noise LDO Features
    5. 2.5 Selecting the Logic Supply Voltage
  4. 3Test Points
    1. 3.1 Voltage Test Points
  5. 4Graphical User Interface
    1. 4.1 TPS650320-Q1 EVM Debugging
      1. 4.1.1 I2C Communication Port and Adapter Debugging
      2. 4.1.2 Updating MCU Firmware
    2. 4.2 Navigating the GUI
      1. 4.2.1 Home
      2. 4.2.2 Block Diagram
      3. 4.2.3 Registers
      4. 4.2.4 Device Configuration
        1. 4.2.4.1 Using Device Configuration to Define Spin Settings
        2. 4.2.4.2 Configuring the Power Sequence
    3. 4.3 Re-Program PMIC
    4. 4.4 In-Circuit Programming
  6. 5Typical Performance Plots
    1. 5.1 Power Sequence Plots
    2. 5.2 Load Transient Plots
    3. 5.3 Output Voltage Ripple Plots
    4. 5.4 Efficiency Plots
    5. 5.5 LDO Output Noise
  7. 6TPS650320-Q1 EVM Schematic
  8. 7TPS650320-Q1 EVM PCB Layers
  9. 8TPS650320-Q1 EVM Bill of Materials

2.4.6 Low Noise LDO Input Supply

Table 2-11 PMIC LDO Power Source (J8)
Selection Jumper PinPMIC LDO Supply Bus
Pin 1 (VSYS)Pin 2 (PMIC LDO Input Supply Rail)
Pin 3 (Buck1 Output Rail - Default)Pin 4 (PMIC LDO Input Supply Rail)
Pin 5 (Buck2 Output Rail)Pin 6 (PMIC LDO Input Supply Rail)
Pin 7 (Buck3 Output Rail)Pin 8 (PMIC LDO Input Supply Rail)