SLVUC17 August   2021 TPS7H2211-SP

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Default Board Configuration
    2. 1.2 Alternate Board Configurations
  3. 2EVM Connectors and Test Points
  4. 3Test Results
    1. 3.1 Default Configuration Results
    2. 3.2 Parallel Configuration Results
  5. 4Board Layout
  6. 5Schematic
    1. 5.1 Default Configuration Schematic
    2. 5.2 Parallel Configuration Schematic
  7. 6Bill of Materials (BOM)
    1. 6.1 Default Configuration BOM
    2. 6.2 Parallel Configuration BOM

Board Layout

Figure 4-1 through Figure 4-7 show the layout of the TPS7H2211EVM-CVAL.

GUID-20210225-CA0I-BZND-XPMX-GJJ28MZCMHGF-low.gif Figure 4-1 Top Silkscreen
GUID-20210225-CA0I-GZNC-3GF9-GZH2T2LKR9DW-low.gif Figure 4-2 Top Solder
GUID-20210225-CA0I-Q1LB-WMP4-NRS4CFSPWRZG-low.gif Figure 4-3 Top Layer
GUID-20210225-CA0I-BSXK-MBWZ-7FHK2GMGQKJS-low.gif Figure 4-4 Signal Layer 1
GUID-20210225-CA0I-QMSN-QJ6B-THFVP8C1ZLMG-low.gif Figure 4-5 Signal Layer 2
GUID-20210225-CA0I-J0RQ-J2PZ-1XPG3D84F7LD-low.gif Figure 4-6 Bottom Layer
GUID-20210225-CA0I-3R3C-GGRD-NGD0LMZJ4DNZ-low.gif Figure 4-7 Bottom Solder