SLVUC28 August   2022 TPS544C26

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Description
    2. 1.2 Before You Begin
  4. 2Performance Characteristics
  5. 3Test Point Descriptions
  6. 4Test Setup
  7. 5Fusion I2C Device GUI
    1. 5.1 Opening the I2C Device GUI
    2. 5.2 On and Off Control OPERATION (01h) and ON_OFF_CONFIG (02h)
    3. 5.3 Changing SYS_CONFIG1 (A0h)
    4. 5.4 Changing the Output Voltage
    5. 5.5 Exporting and Importing Configurations
    6. 5.6 Store to and Restore from NVM
  8. 6Schematics
  9. 7PCB Layout
  10. 8BOM

2 Performance Characteristics

Table 2-1 provides a summary of the TPS544C26EVM performance characteristics. The TPS544C26EVM is designed and tested for VIN = 8 V to 16 V. Characteristics are given for an input voltage of VIN = 12 V and output voltage of 1.1 V, unless otherwise specified. The ambient temperature is room temperature (20°C to 25°C) for all measurements, unless otherwise noted.

Table 2-1 TPS544C26EVM Performance Characteristics Summary
SPECIFICATION TEST CONDITIONS MIN TYP MAX UNIT
VIN voltage range 8 12 16 V
PVIN input current PVIN = 12 V, internal VCC/VDRV, IO = 0 A, Pulse-skip mode 15 mA
VCC/VDRV input current External 5-V bias, fSW = 800 kHz, PVIN = 12 V, IO = 35 A 38 mA
Output voltage setpoint Set by VBOOT in (C1h) TEMP_MAX bits <3:0> 1.1 V
Output current range VIN = 8 V to 16 V 0 35 A
Output ripple voltage fSW = 800 kHz, IO = 35 A 12 mVPP
Output rise time Set by (61h) TON_RISE 1 ms
Current limit Set by (46h) IOUT_OC_FAULT_LIMIT 35 A
Switching frequency (fSW) Set by (33h) FREQUENCY_SWITCH 600 800 1200 kHz
Efficiency VIN = 12 V, external 5-V Bias, fSW = 800 kHz, IO = 35 A 87 %
IC case temperature VIN = 12 V, external 5-V bias, fSW = 1.2 MHz, IO = 35 A, 15-minute dwell time 101 °C
Figure 2-1 Efficiency, FCCM, Internal LDO
Figure 2-3 Efficiency, FCCM, External 5-V Bias
Figure 2-5 Efficiency, DCM. Internal LDO
Figure 2-7 Efficiency, DCM, External 5-V Bias
Figure 2-9 Load Regulation, FCCM, Internal LDO
Figure 2-11 Load Regulation, DCM, Internal VCC LDO
Figure 2-13 ENABLE Start-Up Waveform
Figure 2-15 Output Voltage Ripple, 600-kHz FCCM, 35-A Load
Figure 2-17 Output Voltage Ripple, FCCM, No Load
Figure 2-19 Output Voltage Ripple, DCM, 500-mA Load
Figure 2-21 Thermal Characteristics, 600-kHz FCCM, Internal LDO, 35-A Load
Figure 2-23 Thermal Characteristics, 800-kHz FCCM, Internal LDO, 35-A Load
Figure 2-25 Thermal Characteristics, 1.2-MHz FCCM, Internal LDO, 35-A Load
Figure 2-2 Power Dissipation, FCCM, Internal LDO
Figure 2-4 Power Dissipation, FCCM, External 5-V Bias
Figure 2-6 Power Dissipation, DCM, Internal LDO
Figure 2-8 Power Dissipation, DCM, External 5-V Bias
Figure 2-10 Load Regulation, FCCM, External 5-V Bias
Figure 2-12 Load Regulation, DCM, External 5-V Bias
Figure 2-14 ENABLE Shutdown Waveform
Figure 2-16 Output Voltage Ripple, 800-kHz FCCM, 35-A Load
Figure 2-18 Output Voltage Ripple, DCM, No Load
Figure 2-20 Output Voltage Ripple, DCM, 1-A Load
Figure 2-22 Thermal Characteristics, 600-kHz FCCM, External 5-V Bias, 35-A Load
Figure 2-24 Thermal Characteristics, 800-kHz FCCM, External 5-V Bias, 35-A Load
Figure 2-26 Thermal Characteristics, 1.2-MHz FCCM, External 5-V Bias, 35-A Load