SLVUC32B June 2021 – February 2022 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1 , TPS6594-Q1
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This user’s guide describes a power distribution network (PDN), PDN-0B, between two TPS6594-Q1 devices and either DRA829V or TDA4VM processor with independent MCU and Main power rails. This PDN enables board level isolation of the processor MCU and Main voltage resources as required to leverage the processor architecture in implementing two desirable end product features:
This description includes the following to clarify platform system operation:
There are different orderable part numbers (PNs) of the TPS6594-Q1 device available with unique NVM settings to support different end product use cases and processor types. The unique NVM settings for each PMIC device is optimized per PDN design to support different processors, processing loads, SDRAM types, system functional safety levels, and end product features (such as low power modes, processor voltages, and memory subsystems). The NVM settings can be identified by both NVM_ID and NVM_REV registers. Each PMIC device is distinguished by the part number, NVM_ID, and NVM_REV values listed in Table 2-1.
PDN USE CASE | PDN | Orderable Part Number | TI_NVM_ID (TI_NVM_REV) | Orderable Part Number | TI_NVM_ID (TI_NVM_REV) | Error Signal Monitoring |
---|---|---|---|---|---|---|
|
0B | TPS65941212RWERQ1 | 0x12 (0x03) | TPS65941111RWERQ1 | 0x11 (0x03) | Combined MCU and SOC |
0C | TPS65941213RWERQ1 | 0x13 (0x04) | TPS65941111RWERQ1 | 0x11 (0x03) | Dedicated MCU and SOC |