This user’s guide describes a power distribution network (PDN), PDN-0B, between two TPS6594-Q1 devices and either DRA829V or TDA4VM processor with independent MCU and Main power rails. This PDN enables board level isolation of the processor MCU and Main voltage resources as required to leverage the processor architecture in implementing two desirable end product features:

1. MCU processor acts as independent safety monitor (MCU Safety Island) over the Main processing resources to ensure safe system operations.
2. MCU processor maintains minimum system operations (MCU Only) to significantly reduce processor power dissipation thereby extending battery life during stand-by use cases and reducing component temperature.

This description includes the following to clarify platform system operation:

1. PDN power resource connections
2. PDN digital control connections
3. Primary and secondary PMIC default NVM contents
4. PMIC sequencing settings to support different PDN power state transitions for an advanced processor system

PMIC and processor data manuals describe recommended operation, electrical characteristics, external components, package details, register maps, and overall component functionality. In the event of any inconsistency between any user's guide, application report, or other referenced material, the data sheet specification is the definitive source.

There are different orderable part numbers (PNs) of the TPS6594-Q1 device available with unique NVM settings to support different end product use cases and processor types. The unique NVM settings for each PMIC device is optimized per PDN design to support different processors, processing loads, SDRAM types, system functional safety levels, and end product features (such as low power modes, processor voltages, and memory subsystems). The NVM settings can be identified by both NVM_ID and NVM_REV registers. Each PMIC device is distinguished by the part number, NVM_ID, and NVM_REV values listed in Table 2-1.