SLVUC32B June   2021  – February 2022 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1 , TPS6594-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Versions
  4. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  5. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  6. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  7. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 To Suspend-to-RAM (TO_S2R)
  8. 7Impact of NVM Changes
  9. 8References
  10. 9Revision History

6.3.8 TO_ACTIVE

When a trigger causes the TO_ACTIVE sequence to execute, all rails of the PMICs power up in the recommended processor power up sequence as shown in Figure 6-11.

At the beginning of the TO_ACTIVE sequence both PMICs clear SPMI_LP_EN and LPM_EN and set AMUXOUT_EN and CLKMON_EN.

Note: BUCK3 Monitor, mVDDS_DDR_X, monitors the external regulator controlled by GPIO3, EN_DDR_BUCK. Although these occur at the same time, the analog BIST, which first checks the actual voltage being monitored, occurs approximately 3.7 ms after the monitor is enabled. This is a function of the voltage and slew rate of BUCK3 as described in Table 5-3.

GUID-20210204-CA0I-NDPW-NPQ2-MSQNXQTCHZSP-low.gif Figure 6-11 TO_ACTIVE Sequence