SLVUC32B June   2021  – February 2022 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1 , TPS6594-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Versions
  4. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  5. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  6. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  7. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 To Suspend-to-RAM (TO_S2R)
  8. 7Impact of NVM Changes
  9. 8References
  10. 9Revision History

2 Device Versions

There are different orderable part numbers (PNs) of the TPS6594-Q1 device available with unique NVM settings to support different end product use cases and processor types. The unique NVM settings for each PMIC device is optimized per PDN design to support different processors, processing loads, SDRAM types, system functional safety levels, and end product features (such as low power modes, processor voltages, and memory subsystems). The NVM settings can be identified by both NVM_ID and NVM_REV registers. Each PMIC device is distinguished by the part number, NVM_ID, and NVM_REV values listed in Table 2-1.

Table 2-1 Dual TPS6594-Q1 Orderable Part Numbers for Independent MCU and Main PDN System
PDN USE CASE PDN Orderable Part Number TI_NVM_ID (TI_NVM_REV) Orderable Part Number TI_NVM_ID (TI_NVM_REV) Error Signal Monitoring
  • Up to 9 A(1) on the Primary PMIC 3-phase CPU rail
  • Up to 12 A1 on the Secondary PMIC 4-phase CORE rail
  • Up to 3.4 A(1) on the SDRAM, with support for LPDDR4
  • Supports Processor 2 GHz maximum clock with high-speed SERDES operations
  • Supports 32 Gb of LPDDR4 SDRAM with 4266MTs data rate
  • Supports Functional Safety up to ASIL-D level with MCU Safety Island
  • Supports MCU-only and DDR_Retention low power modes
  • Supports I/O level of 3.3 V or 1.8 V
  • Supports optional end product features:
    • Compliant high-speed SD Card memory
    • Compliant USB 2.0 Interface
    • On-board Efuse programming of high security processors
 0B TPS65941212RWERQ1 0x12 (0x03) TPS65941111RWERQ1 0x11 (0x03) Combined MCU and SOC
0C TPS65941213RWERQ1 0x13 (0x04) TPS65941111RWERQ1 0x11 (0x03) Dedicated MCU and SOC
(1) TI recommends having 15% margin between the maximum expected load current and the maximum current allowed per each PMIC output rail.

Note: PDN-0C is recommended for all new designs and designs needing the additional functional safety coverage provided afforded by the GPIO optimizations found in PDN-0C. This document describes PDN-0B.