SLVUC32B June   2021  – February 2022 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1 , TPS6594-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Versions
  4. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  5. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  6. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  7. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 To Suspend-to-RAM (TO_S2R)
  8. 7Impact of NVM Changes
  9. 8References
  10. 9Revision History

7 Impact of NVM Changes

Table 7-1 NVM Changes from revision 2 to revison 3
Change Impact of change
Update NVM revision to 3, see Table 5-2. None.
VCCA overvoltage and undervoltage monitors are masked in the static configuration, see Table 5-8. None. The monitors are unmasked in the PFSM once the enable pin goes high.
BUCK and LDO overvoltage and undervoltage monitors are masked before the monitor is transitioned from the disabled to the enabled state. The corresponding monitors are unmasked just before release of the nRSTOUT/nRSTOUT_SOC. None. These instructions are performed during the power sequences and have no impact on the timing. Additionally, the monitors are unmasked before the system can perform safety relevant functions.
Logic and analog BIST is run at BOOT BIST, see Table 5-10. BIST time is extended to include the logic BIST.
For the TPS65941111, the readback interrupt for the nINT pin is unmasked. Table 5-8 In the event of a readback error on the nINT pin, a MODERATE_ERR_INT occurs resulting in the transition to SAFE_RECOVERY.