SLVUC99A January 2022 – January 2022 DRA829V , TDA4VM , TPS6594-Q1
These settings detail the default configurations for what is monitored by nINT pin. All these settings can be changed though I2C after startup.
Register Name | Field Name | TPS65941213-Q1 | TPS65941111-Q1 | ||
---|---|---|---|---|---|
Value | Description | Value | Description | ||
FSM_TRIG_MASK_1 | GPIO1_FSM_MASK | 0x1 | Masked | 0x1 | Masked |
GPIO1_FSM_MASK_POL | 0x0 | Low; Masking sets signal value to '0' | 0x0 | Low; Masking sets signal value to '0' | |
GPIO2_FSM_MASK | 0x1 | Masked | 0x0 | Not masked | |
GPIO2_FSM_MASK_POL | 0x0 | Low; Masking sets signal value to '0' | 0x0 | Low; Masking sets signal value to '0' | |
GPIO3_FSM_MASK | 0x1 | Masked | 0x1 | Masked | |
GPIO3_FSM_MASK_POL | 0x0 | Low; Masking sets signal value to '0' | 0x0 | Low; Masking sets signal value to '0' | |
GPIO4_FSM_MASK | 0x1 | Masked | 0x1 | Masked | |
GPIO4_FSM_MASK_POL | 0x0 | Low; Masking sets signal value to '0' | 0x0 | Low; Masking sets signal value to '0' | |
FSM_TRIG_MASK_2 | GPIO5_FSM_MASK | 0x1 | Masked | 0x1 | Masked |
GPIO5_FSM_MASK_POL | 0x0 | Low; Masking sets signal value to '0' | 0x0 | Low; Masking sets signal value to '0' | |
GPIO6_FSM_MASK | 0x1 | Masked | 0x1 | Masked | |
GPIO6_FSM_MASK_POL | 0x0 | Low; Masking sets signal value to '0' | 0x0 | Low; Masking sets signal value to '0' | |
GPIO7_FSM_MASK | 0x1 | Masked | 0x1 | Masked | |
GPIO7_FSM_MASK_POL | 0x0 | Low; Masking sets signal value to '0' | 0x0 | Low; Masking sets signal value to '0' | |
GPIO8_FSM_MASK | 0x1 | Masked | 0x1 | Masked | |
GPIO8_FSM_MASK_POL | 0x0 | Low; Masking sets signal value to '0' | 0x0 | Low; Masking sets signal value to '0' | |
FSM_TRIG_MASK_3 | GPIO9_FSM_MASK | 0x1 | Masked | 0x1 | Masked |
GPIO9_FSM_MASK_POL | 0x0 | Low; Masking sets signal value to '0' | 0x0 | Low; Masking sets signal value to '0' | |
GPIO10_FSM_MASK | 0x1 | Masked | 0x1 | Masked | |
GPIO10_FSM_MASK_POL | 0x0 | Low; Masking sets signal value to '0' | 0x0 | Low; Masking sets signal value to '0' | |
GPIO11_FSM_MASK | 0x1 | Masked | 0x1 | Masked | |
GPIO11_FSM_MASK_POL | 0x0 | Low; Masking sets signal value to '0' | 0x0 | Low; Masking sets signal value to '0' | |
MASK_BUCK1_2 | BUCK1_ILIM_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated |
BUCK1_OV_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
BUCK1_UV_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
BUCK2_ILIM_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
BUCK2_OV_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
BUCK2_UV_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
MASK_BUCK3_4 | BUCK3_ILIM_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated |
BUCK3_OV_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
BUCK3_UV_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
BUCK4_OV_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
BUCK4_UV_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
BUCK4_ILIM_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
MASK_BUCK5 | BUCK5_ILIM_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated |
BUCK5_OV_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
BUCK5_UV_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
MASK_LDO1_2 | LDO1_OV_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated |
LDO1_UV_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
LDO2_OV_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
LDO2_UV_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
LDO1_ILIM_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
LDO2_ILIM_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
MASK_LDO3_4 | LDO3_OV_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated |
LDO3_UV_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
LDO4_OV_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
LDO4_UV_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
LDO3_ILIM_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
LDO4_ILIM_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
MASK_VMON | VCCA_OV_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. |
VCCA_UV_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
MASK_GPIO1_8_FALL | GPIO1_FALL_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. |
GPIO2_FALL_MASK | 0x1 | Interrupt not generated. | 0x0 | Interrupt generated | |
GPIO3_FALL_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
GPIO4_FALL_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
GPIO5_FALL_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
GPIO6_FALL_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
GPIO7_FALL_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
GPIO8_FALL_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
MASK_GPIO1_8_RISE | GPIO1_RISE_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. |
GPIO2_RISE_MASK | 0x1 | Interrupt not generated. | 0x0 | Interrupt generated | |
GPIO3_RISE_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
GPIO4_RISE_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
GPIO5_RISE_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
GPIO6_RISE_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
GPIO7_RISE_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
GPIO8_RISE_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
MASK_GPIO9_11 / MASK_GPIO9_10 | GPIO9_FALL_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. |
GPIO9_RISE_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
GPIO10_FALL_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
GPIO11_FALL_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
GPIO10_RISE_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
GPIO11_RISE_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
MASK_STARTUP | NPWRON_START_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. |
ENABLE_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
FSD_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
SOFT_REBOOT_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
MASK_MISC | TWARN_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated |
BIST_PASS_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
EXT_CLK_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
MASK_MODERATE_ERR | BIST_FAIL_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated |
REG_CRC_ERR_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
SPMI_ERR_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
NPWRON_LONG_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
NINT_READBACK_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
NRSTOUT_READBACK_ MASK | 0x0 | Interrupt generated | 0x1 | Interrupt not generated. | |
MASK_FSM_ERR | IMM_SHUTDOWN_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated |
MCU_PWR_ERR_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
SOC_PWR_ERR_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
ORD_SHUTDOWN_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
MASK_COMM_ERR | COMM_FRM_ERR_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated |
COMM_CRC_ERR_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
COMM_ADR_ERR_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated | |
I2C2_CRC_ERR_MASK | 0x0 | Interrupt generated | 0x1 | Interrupt not generated. | |
I2C2_ADR_ERR_MASK | 0x0 | Interrupt generated | 0x1 | Interrupt not generated. | |
MASK_READBACK_ERR | EN_DRV_READBACK_ MASK | 0x0 | Interrupt generated | 0x1 | Interrupt not generated. |
NRSTOUT_SOC_ READBACK_MASK | 0x0 | Interrupt generated | 0x1 | Interrupt not generated. | |
MASK_ESM | ESM_SOC_PIN_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. |
ESM_SOC_RST_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
ESM_SOC_FAIL_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
ESM_MCU_PIN_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
ESM_MCU_RST_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
ESM_MCU_FAIL_MASK | 0x1 | Interrupt not generated. | 0x1 | Interrupt not generated. | |
GENERAL_REG_1 | PFSM_ERR_MASK | 0x0 | Interrupt generated | 0x0 | Interrupt generated |