SLVUC99A January   2022  – January 2022 DRA829V , TDA4VM , TPS6594-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Versions
  4. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  5. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  6. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  7. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  8. 7Application Examples
    1. 7.1 Moving Between States; ACTIVE, MCU ONLY, and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 Runtime Customization
  9. 8References
  10. 9Revision History

5.10 Miscellaneous Settings

These settings detail the default configurations of additional settings, such as spread spectrum, BUCK frequency, and LDO timeout. All these settings can be changed though I2C after startup.

Table 5-10 Miscellaneous NVM Settings
Register NameField NameTPS65941213-Q1TPS65941111-Q1
ValueDescriptionValueDescription
PLL_CTRLEXT_CLK_FREQ0x01.1 MHz0x01.1 MHz
CONFIG_1TWARN_LEVEL0x0130C0x0130C
I2C1_HS0x0Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code.0x0Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code.
I2C2_HS0x0Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code.0x0Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code.
EN_ILIM_FSM_CTRL0x0Buck/LDO regulators ILIM interrupts do not affect FSM triggers.0x0Buck/LDO regulators ILIM interrupts do not affect FSM triggers.
NSLEEP1_MASK0x0NSLEEP1(B) affects FSM state transitions.0x0NSLEEP1(B) affects FSM state transitions.
NSLEEP2_MASK0x0NSLEEP2(B) affects FSM state transitions.0x0NSLEEP2(B) affects FSM state transitions.
CONFIG_2BB_CHARGER_EN0x0Disabled0x0Disabled
BB_VEOC0x02.5V0x02.5V
BB_ICHR0x0100uA0x0100uA
RECOV_CNT_REG_2RECOV_CNT_THR0xf0xf0xf0xf
BUCK_RESET_REGBUCK1_RESET0x00x00x00x0
BUCK2_RESET0x00x00x00x0
BUCK3_RESET0x00x00x00x0
BUCK4_RESET0x00x00x00x0
BUCK5_RESET0x00x00x00x0
SPREAD_SPECTRUM_1SS_EN0x0Spread spectrum disabled0x0Spread spectrum disabled
SS_MODE0x1Mixed dwell0x1Mixed dwell
SS_DEPTH0x0No modulation0x0No modulation
SPREAD_SPECTRUM_2SS_PARAM10x70x70x70x7
SS_PARAM20xc0xc0xc0xc
FREQ_SELBUCK1_FREQ_SEL0x02.2 MHz0x02.2 MHz
BUCK2_FREQ_SEL0x02.2 MHz0x02.2 MHz
BUCK3_FREQ_SEL0x02.2 MHz0x02.2 MHz
BUCK4_FREQ_SEL0x02.2 MHz0x02.2 MHz
BUCK5_FREQ_SEL0x02.2 MHz0x02.2 MHz
FSM_STEP_SIZEPFSM_DELAY_STEP0xb0xb0xb0xb
LDO_RV_TIMEOUT_ REG_1LDO1_RV_TIMEOUT0xf16ms0xf16ms
LDO2_RV_TIMEOUT0xf16ms0xf16ms
LDO_RV_TIMEOUT_ REG_2LDO3_RV_TIMEOUT0xf16ms0xf16ms
LDO4_RV_TIMEOUT0xf16ms0xf16ms
USER_SPARE_REGSUSER_SPARE_10x00x00x00x0
USER_SPARE_20x00x00x00x0
USER_SPARE_30x00x00x00x0
USER_SPARE_40x00x00x00x0
ESM_MCU_MODE_ CFGESM_MCU_EN0x0ESM_MCU disabled.0x0ESM_MCU disabled.
ESM_SOC_MODE_ CFGESM_SOC_EN0x0ESM_SoC disabled.0x0ESM_SoC disabled.
CUSTOMER_NVM_ID_REG CUSTOMER_NVM_ID 0x0 0x0 0x0 0x0
RTC_CTRL_2XTAL_EN0x0Crystal oscillator is disabled0x0Crystal oscillator is disabled
LP_STANDBY_SEL0x0LDOINT is enabled in standby state.0x1Low power standby state is used as standby state (LDOINT is disabled).
FAST_BIST0x0Logic and analog BIST is run at BOOT BIST.0x0Logic and analog BIST is run at BOOT BIST.
STARTUP_DEST0x3ACTIVE0x3ACTIVE
XTAL_SEL0x06 pF0x06 pF
PFSM_DELAY_REG_1PFSM_DELAY10x580x580x00x0
PFSM_DELAY_REG_2PFSM_DELAY20x9d0x9d0x1d0x1d
PFSM_DELAY_REG_3PFSM_DELAY30x00x00x00x0
PFSM_DELAY_REG_4PFSM_DELAY40x00x00x00x0
GENERAL_REG_0 FAST_BOOT_BIST 0x0 LBIST is run during boot BIST 0x0 LBIST is run during boot BIST
GENERAL_REG_1 REG_CRC_EN 0x1 Register CRC enabled 0x1 Register CRC enabled