SLVUC99A January   2022  – January 2022 DRA829V , TDA4VM , TPS6594-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Versions
  4. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  5. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  6. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  7. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  8. 7Application Examples
    1. 7.1 Moving Between States; ACTIVE, MCU ONLY, and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 Runtime Customization
  9. 8References
  10. 9Revision History

5.7 Finite State Machine (FSM) Settings

These settings describe how the PMIC output rails are assigned to various system-level states. Also, the default trigger for each system-level state is described. All these settings can be changed though I2C after startup.

Table 5-7 FSM NVM Settings
Register NameField NameTPS65941213-Q1TPS65941111-Q1
ValueDescriptionValueDescription
RAIL_SEL_1BUCK1_GRP_SEL0x2SOC rail group0x2SOC rail group
BUCK2_GRP_SEL0x2SOC rail group0x2SOC rail group
BUCK3_GRP_SEL0x1MCU rail group0x0No group assigned
BUCK4_GRP_SEL0x1MCU rail group0x0No group assigned
RAIL_SEL_2BUCK5_GRP_SEL0x2SOC rail group0x2SOC rail group
LDO1_GRP_SEL0x1MCU rail group0x0No group assigned
LDO2_GRP_SEL0x1MCU rail group0x2SOC rail group
LDO3_GRP_SEL0x2SOC rail group0x2SOC rail group
RAIL_SEL_3LDO4_GRP_SEL0x1MCU rail group0x2SOC rail group
VCCA_GRP_SEL0x1MCU rail group0x1MCU rail group
FSM_TRIG_SEL_1MCU_RAIL_TRIG0x2MCU power error0x2MCU power error
SOC_RAIL_TRIG0x3SOC power error0x3SOC power error
OTHER_RAIL_TRIG0x1Orderly shutdown0x1Orderly shutdown
SEVERE_ERR_TRIG0x0Immediate shutdown0x0Immediate shutdown
FSM_TRIG_SEL_2MODERATE_ERR_TRIG0x1Orderly shutdown0x1Orderly shutdown