SLVUC99A January 2022 – January 2022 DRA829V , TDA4VM , TPS6594-Q1
Figure 3-1 shows the power mapping between the dual TPS6594-Q1 PMIC power resources and processor voltage domains required to support independent MCU and Main power rails. In this configuration, both PMICs use a 3.3 V input voltage. For Functional Safety applications, there is a protection FET before VCCA that connects to the OVPGDRV pin of the primary PMIC, allowing voltage monitoring of the input supply to the PMICs.
For SD card dual-voltage I/O support (3.3 V and 1.8 V), LDO1 of the TPS65941111-Q1 device can be used. A processor GPIO control signal with a logic high default value is used to set SD VIO to 3.3 V initially. During processor power up, the boot loader SW can set GPIO signal low to select 1.8 V level as needed for high-speed card operation per SD specification. This allows control of the LDO1 voltage without the need for the MCU processor to establish I2C communication with the PMICs during boot from SD card operations.
This PDN uses four discrete power components with three being required and one is optional depending upon end product features. The two TPS22965-Q1 Load Switches connect VCCA_3V3 power rail to supply OV protected 3.3 V to processor I/O domains. Two load switches are required in order to enable isolation between MCU and Main processor sub-sections for MCU Safety Island or MCU Only low power operations. The unused feedback pin, FB_B3, of the TPS65941213 has been configured per NVM settings, Table 5-3, to provide voltage monitoring for VDD_MCUIO_3V3_LS power rail. This enables all of the MCU processor power supply inputs to have voltage monitoring coverage as needed for functional safety ASIL-B and higher systems. The third discrete device is a TPS62813-Q1 Buck Converter which supplies the LPDDR4 SDRAM component with required 1.1V supply. The last discrete power component is an optional TLV73318-Q1 LDO that can be used if an end product uses a high security processor type and desires the capability to program Efuse values on-board. If this feature is not desired, then this LDO can be omitted and processor pins terminated per data manual recommendations.
Table 3-1 identifies which power resources are required to support different system features. In the Active SoC column, there is an additional option for including or excluding the VPP_x(EFUSE) rail. LDO1 and LDO2 of TPS65941111, which support optional SD CARD and USB Interface features, are enabled as part of the power on sequence as shown in Figure 6-11. Even if these System Features are not used, the regulators are energized as part of the power up sequence.
Power Mapping | System Features(1) | |||||||
---|---|---|---|---|---|---|---|---|
Device | Power Resource | Power Rails | Processor and Memory Domains | Active SoC | MCU - only | DDR Retention | SD Card | USB Interface |
TPS65941213-Q1 | BUCK123 | VDD_CPU_AVS | VDD_CPU | R | ||||
FB_B3 | VDDSHVx_MCU (3.3 V) | R | R | |||||
BUCK4 | VDD_MCU_0V85 | VDDAR_MCU, VDD_MCU | R | R | ||||
BUCK5 | VDD_PHY_1V8 | VDDA_1P8_PHYs | R | |||||
LDO1 | VDD1_DDR_1V8 | Mem: VDD1 | R | O(2) | R(2) | |||
LDO2 | VDD_MCUIO_1V8 | VDDSHVx_MCU (1.8 V) | R | R | ||||
Mem: VCC | ||||||||
LDO3 | VDA_DLL_0V8 | VDDA_0P8_PLLs/DLLs | R | |||||
LDO4 | VDA_MCU_1V8 | VDDA_x | R | R | ||||
TPS65941111-Q1 | BUCK1234 | VDD_CORE_0V8 | VDD_CORE, VDDA_0P8_PHYs | R | ||||
BUCK5 | VDD_RAM_0V85 | VDDAR_CPU/CORE | R | |||||
LDO1 | VDD_SD_DV | VDDSHV5 | R | |||||
LDO2 | VDD_USB_3V3 | VDDA_3P3_USB | R | |||||
LDO3 | VDD_IO_1V8 | VDDS_MMC0 | R | |||||
Mem: VCCQ | ||||||||
LDO4 | VDA_PLL_1V8 | VDDA_1P8_PLLs | R | |||||
TPS22965-Q1 | Load Switch | VDD_MCUIO_3V3 | VDDSHVx_MCU (3.3 V) | R | R | |||
TPS22965-Q1 | Load Switch | VDD_IO_3V3 | VDDSHV0-4,VDDSHV6 (3.3 V) | R | ||||
TLV73318P-Q1 | LDO | VPP_EFUSE_1V8 | VPP_x(EFUSE) | O | ||||
TPS62813-Q1 | BUCK | VDD_DDR_1V1 | VDDS_DDR_BIAS, VDDS_DDR_IO | R | O(3) | R(3) | ||
Mem: VDD2 |