SLVUCD2 January   2022 TPS65917-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2BOOT OTP Configuration
  4. 3Static Platform Settings
    1. 3.1 System Voltage Monitoring
    2. 3.2 SMPS
    3. 3.3 LDO
    4. 3.4 Interrupts
    5. 3.5 GPIO
    6. 3.6 MISC
    7. 3.7 SWOFF_HWRST
    8. 3.8 Shutdown_ColdReset
  5. 4Sequence Platform Settings
    1. 4.1 OFF2ACT Sequences
    2. 4.2 ACT2OFF Sequences

3.6 MISC

This section describes miscellaneous device configuration settings including pulldowns, polarity of signals, communication settings, and other functionality.

Table 3-11 MISC1 OTP Settings
REGISTERBITDESCRIPTIONOTP VALUE
PU_PD_INPUT_CTRL1RESET_IN_PDEnable and disable internal pulldown for the RESET_IN pin1: Pulldown enabled
PWRDOWN_PDEnable and disable internal pulldown for the PWRDOWN pin1: Pulldown enabled
Table 3-12 MISC2 OTP Settings
REGISTERBITDESCRIPTIONOTP VALUE
I2C_SPII2C_SPISelection of control interface, I2C, or SPI0: I2C
ID_I2C2I2C_2 address for page access versus initial address (0H12)0: Address is 0x12
ID_I2C1I2C_1 address for I2C register accessI2C_1[0] = 1: 0x58
I2C_1[1] = 1: 0x59
I2C_1[2] = 1: 0x5A
I2C_1[3] = 1: 0x5B
PMU_CONFIGHIGH_VCC_SENSEEnable internal buffers on VCC_SENSE to allow voltage sensing above 5.25 V0: High VCC sense not enabled
AUTODEVONAutomatically set DEV_ON bit after startup sequence completes0: AUTODEVON
disabled
SWOFF_DLYDelay before switch-off to allow host processor to save context. Device is maintained as ACTIVE until delay expiration then switches off.00: No delay
PMU_CTRL2INT_LINE_DISConfigure INT output to be standard buffer or high-impedance buffer with pullup to VIO0: Standard buffer: open-drain or push-pull
WDT_HOLD_IN_SLEEPConfigure watchdog timer operation during device sleep state1: Watchdog timer does not run in sleep state
PWRDOWN_FASTOFFConfigure shut-down sequence from PWRDOWN pin event0: PWRDOWN pin event triggers sequenced shut down
TSHUT_FASTOFFConfigure shut-down sequence from thermal shutdown event0: Thermal shutdown triggers sequenced shut down
OD_OUTPUT_CTRL2RESET_OUT_ODConfigure RESET_OUT to be push-pull or open-drain1: RESET_OUT is open-drain
REGEN2_ODConfigure REGEN2 to be push-pull or open-drain1: REGEN2 is open-drain
PMU_SECONDARY_INTFSD_MASKSecondary level of mask for FSD interrupt line1: FSD_INT_SRC is masked
POLARITY_CTRLINT_POLARITYConfigure polarity of INT line0: INT line is low when interrupt is pending
PRIMARY_SECONDARY_PAD2SYNCCLKOUTConfigure SYNCCLKOUT to output SYNCDCDCCLK or CLK32KGO0: SYNCDCDCCLK