This User’s Guide can be used as a guide for integrating the TPS65941515-Q1 power management integrated circuit (PMIC) into a system powering the Automotive Jacinto™ 7 DRA821 processor.
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This user’s guide describes a power distribution network (PDN), PDN-2A, using a single TPS6594-Q1 PMIC and a few discrete components to power the DRA821 processor and peripherals.
The following topics are described to clarify platform system operation:
There are different versions of the TPS6594-Q1 device available with unique NVM settings to support different processor solutions. The unique NVM settings for each PMIC device are optimized per PDN design to support different processors, processing loads, SDRAM types, system functional safety levels, and end product features (such as low power modes, processor voltages, and memory subsystems). The NVM settings can be identified by both the TI_NVM_ID and NVM_REV registers.
PDN USE CASE | Orderable Part Number | TI_NVM_ID | TI_NVM_REV |
---|---|---|---|
|
TPS65941515 | 0x15 | 0x03 |
This section details how the TPS65941515-Q1 power resources and GPIO signals are connected to the processor and other peripheral components.