This User’s Guide can be used as a guide for integrating the TPS65941515-Q1 power management integrated circuit (PMIC) into a system powering the Automotive Jacinto™ 7 DRA821 processor.
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This user’s guide describes a power distribution network (PDN), PDN-2A, using a single TPS6594-Q1 PMIC and a few discrete components to power the DRA821 processor and peripherals.
The following topics are described to clarify platform system operation:
There are different versions of the TPS6594-Q1 device available with unique NVM settings to support different processor solutions. The unique NVM settings for each PMIC device are optimized per PDN design to support different processors, processing loads, SDRAM types, system functional safety levels, and end product features (such as low power modes, processor voltages, and memory subsystems). The NVM settings can be identified by both the TI_NVM_ID and NVM_REV registers.
PDN USE CASE | Orderable Part Number | TI_NVM_ID | TI_NVM_REV |
---|---|---|---|
|
TPS65941515 | 0x15 | 0x03 |
This section details how the TPS65941515-Q1 power resources and GPIO signals are connected to the processor and other peripheral components.
Figure 3-1 shows the power mapping between the TPS65941515-Q1 PMIC and peripheral regulators to power the processor and associated accessories. In this configuration, the PMIC and additional resources use a 3.3 V input voltage. For Functional Safety applications, there is a protection FET before VCCA that connects to the OVPGDRV pin of the PMIC, allowing voltage monitoring of the input supply to the system.
This PDN uses five discrete power components with four being required and one is optional depending upon end product features. The two TPS22965-Q1 Load Switches connect VCCA_3V3 power rail to supply 3.3 V to processor I/O domains. The third discrete device is a TPS274501-Q1 LDO is used to supply power in low-power retention mode. The fourth discrete device is a TLV73318-Q1 LDO which supplies the LPDDR4 SDRAM component with required 1.8V supply. The last discrete power component is an optional TLV73318-Q1 LDO that can be used if an end product uses a high security processor type and desires the capability to program EFUSE values on-board. If this feature is not desired, then this LDO can be omitted and processor pins terminated per data manual recommendations.
Table 3-1 identifies which power resources are required to support different system features. In the Active SoC column, there is an additional option for including or excluding the VPP_x(EFUSE) rail.
Power Mapping | System Features(1) | |||||||
---|---|---|---|---|---|---|---|---|
Device | Power Resource | Power Rails | Processor and Memory Domains | Active SoC |
GPIO Retention |
DDR Retention | SD Card | USB Interface |
TPS65941515-Q1 | BUCK12 | VDD_CPU_AVS | VDD_CPU | R | ||||
BUCK34 |
VDD_CORE_0V8 |
VDD_MCU, VDDA_SERDES |
R | |||||
BUCK5 | VDD_DDR_1V1 |
VDDS_DDR |
R |
R |
||||
Mem: LPDDR4_VDD2 and VDDQ |
||||||||
LDO1 | VDD_IO_1V8 | VDDS_MMC0, VDDSHVx_MCU(1.8V) | R | |||||
Mem: VCC |
||||||||
LDO2 | VDD_RAM_0V85 |
VDDAR_MCU, VDDAR_CPU/CORE |
R | |||||
LDO3 | VDA_DPLL_0V8 | VDDA_0P8_PLLs/DLLs | R | |||||
LDO4 | VDA_LN_1V8 | VDDA_x(1.8V) | R | |||||
TPS22965-Q1 | Load Switch-A | VDD_IO_3V3 | VDDSHVx_MCU (3.3 V), VDDSHV0, VDDSHV5 |
R |
R |
R |
||
Mem: EMMC VCC |
||||||||
TPS22965-Q1 | Load Switch-B | VDD_GPIORET_3V3 | VDDSHV0-4,VDDSHV6 (3.3 V) | R |
R |
|||
TPS74501P-Q1 |
LDO-A |
VDD_WK_0V8 |
VDDSHV2 |
R |
R |
|||
TLV73318P-Q1 | LDO-B |
VDD1_LPDDR4_1V8 |
Mem: LPDDR4_VDD1 |
R |
||||
TLV73318P-Q1 | LDO-C |
VPP_EFUSE_1V8 |
VPP_x(EFUSE) |
O |