SLVUCD4 November   2022 TPS6594-Q1

 

  1.   PDN-2A User's Guide for Powering DRA821 with TPS65941515-Q1 PMIC
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  6. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 TO_ACTIVE
      5. 6.3.5 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States: ACTIVE and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 GPIO8 and Watchdog
  10. 8References

4.2 Achieving up to ASIL-D System Requirements

For ASIL-C or ASIL-D systems, the following features in addition to the ones described in Section 4.1 can be used:

  • PMIC current monitoring on all output power rails
  • SoC error monitoring
  • Residual Voltage Monitoring
  • Read-back of Logic Output Pins
    • nINT
    • nRSTOUT
    • EN_DRV (when used)
The current monitoring is enabled by default for all BUCKs and LDOs for the PMIC. Additionally, Figure 3-1 shows that the MCU domain of the processor is powered by different power resources of the PMICs than the main power domain of the processor.

GPIO_3 is configured as the SoC error signal monitor. Similar to the MCU error signal monitor, this feature is enabled through I2C using the ESM_SOC_EN register bit. For the TPS65941515, an SoC reset is not supported but an interrupt fires and the nINT pin driven low.

Table 4-1 System Level Safety Features
ASIL-BASIL-D
External SW WdogINTn

Safety MCU Processing ESM

Safety MCU Reset

Safety Status SignalSystem Input Voltage Monitoring

SoC Main Processing ESM

IO Read-Back Feature
Q&A Watchdog and I2C2

nINT Pin

nERR_MCU connected to SOC:MCU_SAFETY_ERRz

nRSTOUT connected to MCU_PORz_1V8

ENDRVVSYS_SENSE -OV with Safety FET OVPGDRV

VCCA OV & UV and

nERR_SoC connected to SOC: SOC_SAFETY_ERRz

PMICA: nINT, nRSTOUT, EN_DRV

Table 4-2 Power Monitoring Safety Features
ASIL-BASIL-D Adds
DevicePower ResourcePDN Power RailSafe State Power Group1Supply Voltage MonitoringSupply Current MonitoringResidual Voltage Monitoring
TPS65941515-Q1BUCK1-2VDD_CPU_AVS

MCU

OV & UVYES

YES

BUCK3-4VDD_CORE_0V8MCUOV & UVYES

YES

BUCK5VDD_DDR_1V1

MCU

OV & UVYES2

YES

LDO1VDD_IO_1V8

MCU

OV & UV

YES

YES

LDO2VDD_RAM_0V85MCUOV & UV

YES

YES

LDO3VDA_DPLL_0v8

MCU

OV & UV

YES

YES

LDO4VDA_LN_1V8MCUOV & UV

YES

YES

TPS22965W-Q1Ld Sw AVDD_IO_3V3

None

NO

NO3
TPS22965W-Q1Ld Sw BVDD_GPIORET_3V3

None

NO

NO4

TLV73318P-Q1

LDO-A

VDD1_LPDDR4_1V8

None

NO

2		NO2

TPS74501P-Q1

LDO-B

VDD_WK_0V8

None

NONO
TLV73318P-Q1LDO-CVPP_EFUSE_1V8NoneNO5NO5
  1. Rail Group settings for the TPS65941515-Q1 are found in Table 5-7.
  2. Power rails VDD_DDR_1V1 and VDD1_LPDDR4_1V8 are safety critical but do not required direct voltage or current monitoring since other means are available (for example, SoC internal timeout gaskets and ECC checkers) provide diagnostic coverage to detect faults in the DDR voltage.
  3. Power rails VDD_IO_1V8/3V3 is typically not safety critical since other means are available (for example, black-channel checkers) to provide diagnostic coverage to detect faults in SoC signaling interfaces (for example, CAN, UART, and SPI).
  4. If an SoC GPIO control signal is used in a safety critical interface, then adding voltage and current monitoring to specific VIO power rail may be needed per customer's end product design.
  5. Power rail VPP_EFUSE_1V8 is not safety critical since Efuse programming does not occur during safety critical processing.