SLVUCD4 November   2022 TPS6594-Q1

 

  1.   PDN-2A User's Guide for Powering DRA821 with TPS65941515-Q1 PMIC
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  6. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 TO_ACTIVE
      5. 6.3.5 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States: ACTIVE and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 GPIO8 and Watchdog
  10. 8References

6.2 PFSM Triggers

As shown in Figure 6-1, there are various triggers that can enable a state transition between configured states. Table 6-1 describes each trigger and its associated state transition from highest priority (Immediate Shutdown) to lowest priority (I2C_3). Active triggers of higher priority block triggers of lower priority and the associated sequence.

Table 6-1 State Transition Triggers
TriggerPriority (ID)Immediate (IMM)REENTERANTPFSM Current StatePFSM Destination StatePower Sequence or Function Executed
Immediate Shutdown

1

TrueFalseSTANDBY, ACTIVE, Suspend-to-RAMSAFE(1)TO_SAFE_SEVERE

MCU Power Error

2

True

False

STANDBY, ACTIVE, Suspend-to-RAMSAFE(1)

TO_SAFE

Orderly Shutdown

4

TrueFalseSTANDBY, ACTIVE, Suspend-to-RAMSAFE(1)TO_SAFE_ORDERLY
OFF Request

5

FalseFalseSTANDBY, ACTIVE, Suspend-to-RAMSTANDBY(2)TO_STANDBY
WDOG Error

6

FalseTrueACTIVEACTIVEACTIVE_TO_WARM

ESM MCU Error

7

False

True

ACTIVE

ACTIVE

I2C_1 bit is high(3)8FalseTrueACTIVENo State ChangeExecute RUNTIME BIST
I2C_2 bit is high(3)9FalseTrueACTIVENo State ChangeEnable I2C CRC on I

2

C1 and I

2

C2 on all devices.
ON Request10FalseFalseSTANDBY, ACTIVE, Suspend-to-RAMACTIVETO_ACTIVE
WKUP1 goes high11FalseFalseSTANDBY, ACTIVE, Suspend-to-RAMACTIVE
NSLEEP1 and NSLEEP2 are high(4)12FalseFalseSTANDBY, ACTIVE, Suspend-to-RAMACTIVE
NSLEEP1 goes low and NSLEEP2 goes high(4)

13

FalseFalseACTIVE, Suspend-to-RAM

No State Change

No Sequence Executed

NSLEEP1 goes low and NSLEEP2 goes low(4)14FalseFalseACTIVESuspend-to-RAMTO_RETENTION
NSLEEP1 goes high and NSLEEP2 goes low(4)15FalseFalseACTIVESuspend-to-RAM
I2C_0 bit goes high(3)16FalseFalseSTANDBY, ACTIVELP_STANDBY(2)TO_STANDBY
I2C_3 bit goes high(3)17FalseFalseACTIVENo State ChangeDevices are prepared for OTA NVM update.(5)
(1) From the SAFE state, the PFSM automatically transitions to the hardware FSM state of SAFE_RECOVERY. From the SAFE_RECOVERY state, the recovery counter is incremented and compared to the recovery count threshold (see RECOV_CNT_REG_2, in Table 5-10). If the recovery count threshold is reached, then the PMIC halts recovery attempts and requires a power cycle. Refer to the data sheet for more details.
(2) If the LP_STANDBY_SEL bit is set (see RTC_CTRL_2, in Table 5-10), then the PFSM transitions to the hardware FSM state of LP_STANDBY. When LP_STANDBY is entered, then please use the appropriate mechanism to wakeup the device as determined by the means of entering LP_STANDBY. Refer to the data sheet for more details.
(3) I2C_0, I2C_1, I2C_2 and I2C_3 are self-clearing triggers.
(4) NSLEEP1 and NSLEEP2 of the PMIC can be accessed through the GPIO pin or through a register bit. If either the register bit or the GPIO pin is pulled high, the NSLEEPx value is read as a high logic level.
(5) After completion of an OTA update, the processor is required to initiate a reset of the PMICs to apply the new NVM settings.