SLVUCE3 april 2023 TPS54KB20
4.1 Layout
The board layout for the TPS54KB20EVM is shown in Figure 4-21 through Figure 4-8. The top-side layer of the EVM is laid out in a manner typical of a user application. The top, bottom, and internal layers are 2-oz. copper. The small size U1 circuit takes up an area of only approximately 250 mm2 as shown on the silkscreen.
Figure 4-1 Top-Side Composite View
Figure 4-3 Top
Layer Layout
Figure 4-5 Mid
Layer 2 Layout
Figure 4-7 Mid Layer 4 Layout
Figure 4-2 Bottom-Side Composite View (Viewed From
Bottom)
Figure 4-4 Mid
Layer 1 Layout
Figure 4-6 Mid Layer 3 Layout
Figure 4-8 Bottom Layer Layout