SLVUCE3 april   2023 TPS54KB20

 

  1.    TPS54KB20EVM 25-A, Regulator Evaluation Module
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Background
    2. 1.2 Before You Begin
    3. 1.3 Performance Characteristics Summary
  4. 2Configurations and Modifications
    1. 2.1 Output Voltage
    2. 2.2 Frequency and Operation Mode Setting (MSEL Pin)
  5. 3Test Setup and Results
    1. 3.1 Input/Output Connections
    2. 3.2 Efficiency
    3. 3.3 Output Voltage Regulation
    4. 3.4 Load Transient and Loop Response
    5. 3.5 Output Voltage Ripple
    6. 3.6 Start-up and Shutdown with EN
    7. 3.7 Thermal Performance
  6. 4Board Layout
    1. 4.1 Layout
  7. 5Schematic and Bill of Materials
    1. 5.1 Schematic
    2. 5.2 Bill of Materials

Layout

The board layout for the TPS54KB20EVM is shown in Figure 4-21 through Figure 4-8. The top-side layer of the EVM is laid out in a manner typical of a user application. The top, bottom, and internal layers are 2-oz. copper. The small size U1 circuit takes up an area of only approximately 250 mm2 as shown on the silkscreen.

GUID-20230329-SS0I-T7SJ-7BGF-54QDVM6BZXV5-low.svgFigure 4-1 Top-Side Composite View
GUID-20230329-SS0I-JNFQ-JRQR-WQ2DGPVGJ1BQ-low.svgFigure 4-3 Top Layer Layout
GUID-20230329-SS0I-JDLK-P0K7-PQ8DCNRMB2R8-low.svgFigure 4-5 Mid Layer 2 Layout
GUID-20230329-SS0I-M1RF-PZD6-PF51KLM9MFXL-low.svgFigure 4-7 Mid Layer 4 Layout
GUID-20230329-SS0I-89RX-QHV4-CPPCL0DCGKR8-low.svgFigure 4-2 Bottom-Side Composite View (Viewed From Bottom)
GUID-20230329-SS0I-MMCL-N3FW-Z2XNJHBTBZTM-low.svgFigure 4-4 Mid Layer 1 Layout
GUID-20230329-SS0I-29LZ-FH8F-ZRSVDPTMV6H9-low.svgFigure 4-6 Mid Layer 3 Layout
GUID-20230329-SS0I-WGRK-L0ZB-PFVMN9HJDMVN-low.svgFigure 4-8 Bottom Layer Layout