SLVUCE3 april   2023 TPS54KB20

 

  1.    TPS54KB20EVM 25-A, Regulator Evaluation Module
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Background
    2. 1.2 Before You Begin
    3. 1.3 Performance Characteristics Summary
  4. 2Configurations and Modifications
    1. 2.1 Output Voltage
    2. 2.2 Frequency and Operation Mode Setting (MSEL Pin)
  5. 3Test Setup and Results
    1. 3.1 Input/Output Connections
    2. 3.2 Efficiency
    3. 3.3 Output Voltage Regulation
    4. 3.4 Load Transient and Loop Response
    5. 3.5 Output Voltage Ripple
    6. 3.6 Start-up and Shutdown with EN
    7. 3.7 Thermal Performance
  6. 4Board Layout
    1. 4.1 Layout
  7. 5Schematic and Bill of Materials
    1. 5.1 Schematic
    2. 5.2 Bill of Materials

3.2 Efficiency

Figure 3-2 through Figure 3-4 show the efficiency for both designs on the TPS54KB20EVM. The test points listed in Table 3-3 are used for the efficiency measurement. Use these test points to minimize the contribution of PCB parasitic power loss to the measured power loss.

The following are some additional test setup considerations to minimize external sources of power dissipation.

  • Disable the other regulator to avoid including the switching quiescent current of the other regulator in the efficiency measurement.
  • Do not measure the SW pin of U2 with TP28 while measuring the efficiency of U2. Measuring the SW pin with this test point loads this node with 500 Ω and the efficiency measurement includes the power lost in this external resistance.

Table 3-3 Efficiency Measurement Test Points
RELATED ICTEST POINT NAMEREFERENCE DESIGNATORFUNCTION
U1VIN1TP1Input voltage test point connected near pins of U1
PGND1 TP9 PGND reference test point for input voltage
REG_VOUT1TP8Output voltage test point near output inductor of U1
PGND1TP4PGND reference test point for output voltage
U2VIN2TP12Input voltage test point connected near pins of U2
PGND2 TP24 PGND reference test point for input voltage
REG_VOUT2TP20Output voltage test point near output inductor of U2
REG_GNDTP17PGND reference test point for output voltage
GUID-20230405-SS0I-DWJX-FR8Z-VHNRLWNHHTHS-low.svgFigure 3-2 U1 Efficiency – Skip-Mode (Default)
GUID-20230405-SS0I-HXZR-ZWNH-MFPRTWSZ5HDN-low.svgFigure 3-4 U2 Efficiency – FCCM
GUID-20230405-SS0I-9BVR-BTXK-JZVHHJZCTWGZ-low.svgFigure 3-3 U2 Efficiency – Skip-Mode (Default)