SLVUCH7A september 2022 – june 2023 TPS25990
- 1
- TPS25990EVM: Evaluation Module for TPS25990 eFuse
- Trademarks
- 1Introduction
- 2Description
- 3Schematic
- 4General Configurations
-
5Test Setup and Procedures
- 5.1 Hot Plug
- 5.2 Start-up with Enable
- 5.3 Current Limit Based Start-up Behavior
- 5.4 Power Up into Short
- 5.5 Overvoltage Lockout
- 5.6 Transient Overload Performance
- 5.7 Overcurrent Event
- 5.8 Provision to Apply Load Transient and Overcurrent Event Using an Onboard Switching Circuit
- 5.9 Output Hot Short
- 5.10 Quick Output Discharge (QOD)
- 5.11 Thermal Performance of TPS25990EVM
- 6Using the TPS25990EVM-GUI
- 7EVAL Board Assembly Drawings and Layout Guidelines
- 8Bill Of Materials (BOM)
- 9Revision History
7.1 PCB Drawings
Figure 7-1 and Figure 7-2 show the component placements of the EVM. A pictorial representation of the TPS25990EVM PCB layers can be found in Figure 7-3 to Figure 7-10.
Figure 7-1 TPS25990EVM Board: Top
Assembly
Figure 7-3 TPS25990EVM Board: Top
Layer
Figure 7-5 TPS25990EVM Board: Layer 2
(Power)
Figure 7-7 TPS25990EVM Board: Layer 4
(Signal)
Figure 7-9 TPS25990EVM Board: Layer 6
(Power)
Figure 7-2 TPS25990EVM Board: Bottom
Assembly
Figure 7-4 TPS25990EVM Board: Bottom
Layer
Figure 7-6 TPS25990EVM Board: Layer 3
(Power)
Figure 7-8 TPS25990EVM Board: Layer 5
(Signal)
Figure 7-10 TPS25990EVM Board: Layer 7
(Power)Note: Analog signal nets, such as IREF, IMON, and TEMP, need to be routed away as much as possible from power nets such as VIN, VOUT, and PGND.