SLVUCI4B february   2023  – may 2023 TPS7H5001-SP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2System Design Theory
    1. 2.1  Switching Frequency
    2. 2.2  Leading Edge Blanking
    3. 2.3  Dead Time
    4. 2.4  Enable and UVLO
    5. 2.5  Output Voltage Programing
    6. 2.6  Soft Start
    7. 2.7  Sensing Circuit
    8. 2.8  FAULT Mode
    9. 2.9  HICCUP Mode
    10. 2.10 Slope Compensation
    11. 2.11 Output Capacitance
    12. 2.12 Compensation
  6. 3Test Results
  7. 4Bill of Materials
  8. 5Schematics
  9. 6PCB Layouts
  10. 7References
  11. 8Revision History

Test Results

GUID-20221206-SS0I-4BTW-KMKQ-HSHPNL2QVF1D-low.svg Figure 3-1 Efficiency vs. Current
GUID-20221206-SS0I-JZR4-NHZG-3XXXSWQRTDHP-low.png Figure 3-2 Start-up Unloaded

Figure 3-2 shows start-up of the converter when unloaded. The first 4 ms of start-up are choppy due to the minimum on-time of the converter. When the minimum on-time of the converter is smaller than the duty cycle used during parts of start-up choppiness can occur.

GUID-20221206-SS0I-GDFZ-CDJW-JZF1W7LFF1LW-low.png Figure 3-3 Start-up Loaded

Figure 3-3 shows start-up of the converter when loaded with 20 A for the output current. The first 4 ms of start-up are choppy due to the minimum on-time of the converter. When the minimum on-time of the converter is smaller than the duty cycle used during parts of start-up choppiness will occur.

GUID-20221206-SS0I-JZZQ-7X0Z-SZLWG7K0LBWD-low.png Figure 3-4 Shutdown

Figure 3-4 shows shutdown of the converter when loaded with 20 A on the output current.

GUID-20221206-SS0I-021T-VMNC-25VBGTVTCJRP-low.png Figure 3-5 Output Voltage Ripple

Figure 3-5 shows the output voltage ripple with an output current of 20 A.

GUID-20221206-SS0I-XCM5-B4ZK-XBTHCDKWFQJB-low.png Figure 3-6 Positive Load Step

Figure 3-6 shows the output voltage dip of the converter to a 6.67 positive output current transient.

GUID-20221206-SS0I-RNF2-V5HH-MKZC43C2WRRF-low.png Figure 3-7 Negative Voltage Transient

Figure 3-7 shows the output voltage dip of the converter to a 6.67 positive output current transient.

GUID-20221206-SS0I-VSXK-TP5P-XQQLHQZZVNPX-low.jpg Figure 3-8 Thermal Image of Board with 20 A Output Current

Figure 3-8 shows the thermal image of the board with 20 A output current. The main hot spot of the picture is the bottom side GaN FET. This is the main limiter of the output current. It is suggested to achieve a larger output current that a second GaN FET be put in parallel on the bottom side.

GUID-20221206-SS0I-WG7N-LXGF-WM63PZB1BZZR-low.png Figure 3-9 Frequency Response
GUID-20221206-SS0I-J1J0-KZWN-V6LXF2KXV9KD-low.png Figure 3-10 Switch Node Voltage with Full Output Current

Figure 3-10 shows the maximum voltage on the switch node of the converter with an output current of 20 A.