SLVUCI5 april   2023 AM6526 , AM6528 , AM6548 , TPS6594-Q1

 

  1.   PDN-0C User's Guide for Powering AM65x with the TPS6594-Q1 PMIC
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  6. 4Supporting Functional Safety Systems
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States; ACTIVE, MCU ONLY, and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 Runtime Customization
  10. 8References

6.3.1 TO_SAFE_SEVERE and TO_SAFE

The TO_SAFE_SEVERE and TO_SAFE are distinct sequences which occur when transition to the SAFE state. Both sequences shut down all rails without delay. The TO_SAFE_SEVERE sequence immediately ceases BUCK switching and enables the pulldown resistors of the BUCKs and LDOs. The cessation of BUCK switching is to prevent any damage of the PMICs in case of over voltage on VCCA or thermal shutdown. The timing is illustrated in Figure 6-2. The TO_SAFE sequence does not reset the BUCK regulators until after the regulators are turned off.

GUID-20220701-SS0I-1LCF-PBD7-HMZTRWW2ZFBF-low.svg Figure 6-2 TO_SAFE_SEVERE and TO_SAFE Power Sequences

After the power sequence shown in Figure 6-2, the TO_SAFE sequence delays the sequence by 16 ms. After this delays, the following instructions are executed:


// Clear AMUXOUT_EN, CLKMON_EN, set LPM_EN
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xE3
// Reset all BUCK regulators
REG_WRITE_MASK_IMM ADDR=0x87 DATA=0x1F MASK=0xE0
// Make GPIO9 an input with pulldown enabled
REG_WRITE_MASK_IMM ADDR=0x39 DATA=0x18 MASK=0x00
// Make GPIO10 an input with pulldown enabled
REG_WRITE_MASK_IMM ADDR=0x3A DATA=0x08 MASK=0x00

The TO_SAFE_SEVERE sequence executes the following instruction after the power sequence:


// Clear AMUXOUT_EN, CLKMON_EN, set LPM_EN
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xE3
// Make GPIO9 an input with pulldown enabled
REG_WRITE_MASK_IMM ADDR=0x39 DATA=0x18 MASK=0x00
// Make GPIO10 an input with pulldown enabled
REG_WRITE_MASK_IMM ADDR=0x3A DATA=0x08 MASK=0x00
A delay of 500 ms is at the end of the TO_SAFE_SEVERE sequence. The recovery is not attempted until after the sequence delay is complete.