SLVUCI5 april 2023 AM6526 , AM6528 , AM6548 , TPS6594-Q1
These settings describe how the PMIC output rails are assigned to various system-level states. Also, the default trigger for each system-level state is described. All these settings can be changed though I2C after startup.
Register Name | Field Name | TPS65941319-Q1 | |
---|---|---|---|
Value | Description | ||
RAIL_SEL_1 | BUCK1_GRP_SEL | 0x2 | SOC rail group |
BUCK2_GRP_SEL | 0x2 | SOC rail group | |
BUCK3_GRP_SEL | 0x2 | SOC rail group | |
BUCK4_GRP_SEL | 0x1 | MCU rail group | |
RAIL_SEL_2 | BUCK5_GRP_SEL | 0x1 | MCU rail group |
LDO1_GRP_SEL | 0x1 | MCU rail group | |
LDO2_GRP_SEL | 0x2 | SOC rail group | |
LDO3_GRP_SEL | 0x2 | SOC rail group | |
RAIL_SEL_3 | LDO4_GRP_SEL | 0x2 | SOC rail group |
VCCA_GRP_SEL | 0x1 | MCU rail group | |
FSM_TRIG_SEL_1 | MCU_RAIL_TRIG | 0x2 | MCU power error |
SOC_RAIL_TRIG | 0x3 | SOC power error | |
OTHER_RAIL_TRIG | 0x1 | Orderly shutdown | |
SEVERE_ERR_TRIG | 0x0 | Immediate shutdown | |
FSM_TRIG_SEL_2 | MODERATE_ERR_TRIG | 0x1 | Orderly shutdown |