Figure 3-1 shows the power mapping between the TPS6594-Q1 PMIC power resources and processor voltage domains required to support independent MCU and Main power rails. In this configuration, the PMIC uses a 3.3 V input voltage. For safety applications, there is a protection FET before VCCA that connects to the OVPGDRV pin of the primary PMIC, allowing voltage monitoring and control of the input supply to the PMICs.

This PDN uses five discrete power components with four being required and one is optional depending if the efuse feature is needed. The three load switches in addition to the BUCK4 regulator create independent IO power rails with the following benefits:

1. Sequencing SoC power domains in desired order by using PMIC GPIO control signals with desired start‐up & shut‐down timing delays shown in the Section 6.3 section.
2. PMIC monitoring of VCCA Over Voltage (see Section 5.5) allows PMIC GPIOs to disconnect these 3.3V power rails from SoC if OV is detected.
3. Required for low power modes (MCU Only and S2R Retention) since disabling/monitoring the IO domain of the SoC independently is required.

The fourth discrete device is a TPS628502 Buck Converter which supplies the LPDDR4 SDRAM component with required 1.1V supply. The last discrete power component is an optional TLV70018-Q1 LDO that can be used if an end product uses a high security processor type and desires the capability to program Efuse values on-board. If this feature is not desired, then this LDO can be omitted and processor pins terminated per data manual recommendations.

Figure 3-1 Power Connections

• VDD_CPU_AVS, boot voltage of 1.1 V then software sets device specific AVS.

Table 3-1 identifies which power resources are required to support different system features. In the Active SoC column, there is an additional option for including or excluding the VPP_x(EFUSE) rail.