SLVUCI5 april   2023 AM6526 , AM6528 , AM6548 , TPS6594-Q1

 

  1.   PDN-0C User's Guide for Powering AM65x with the TPS6594-Q1 PMIC
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  6. 4Supporting Functional Safety Systems
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States; ACTIVE, MCU ONLY, and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 Runtime Customization
  10. 8References

3.2 Control Mapping

Figure 3-2 shows the digital control signal mapping between processor and PMIC devices. Connections from the TPS6594-Q1 PMICs to the processor provide error monitoring, processor reset, processor wake up, and system low-power modes.

The digital connections shown in Figure 3-2 allow system features including 'MCU-only, MCU Safety Island' and Retention modes, and functional safety up to SIL-3.

GUID-20220701-SS0I-Z6ZD-J1ZV-ZRGMFCXCJQVT-low.svg Figure 3-2 TPS6594-Q1 Digital Connections
  1. PMIC IO can have distinct power domains for input and output functionality. The SDA function for I2C1 and I2C2 use the VINT voltage domain as an input and the VIO voltage domain as an output. Please refer to the device data sheet for a complete description.
  2. GPIO8 is configured as the DISABLE_WDOG pin. When the PMIC sets nRSTOUT, the logic level of GPIO8 is latched into the WD_PWRHOLD bit. If low, then the watchdog enters the long window and the processor must service the WDOG before the long window expires or the PMIC performs a warm reset of the processor. Once the WDOG is serviced, then the control of the WDOG can be maintained through the I2C2 and the GPIO8 can be repurposed for WKUP1 or WKUP2. WKUP1 and WKUP2 are not functional from LP_STANDBY.
  3. GPIO9, NSLEEP1 or NSLEEP2, is not connected to the processor and is not part of the PDN. If the customer chooses to use this GPIO, the function must be defined at runtime.
Note: The PMIC voltage domain of an IO can be different depending upon configuration. When configured as an input GPIO3 and GPIO4 are in the VRTC domain. When configured as an output, GPIO3 and GPIO4 are in the VINT domain.
Note: In addition to the I2C signals, four additional signals are open-drain outputs and require a pullup to a specific power rail. Please refer to Table 3-2 for a list of the signals and the specific power rail.
Table 3-2 Open-drain signals and Power Rail
PDN SignalPullup Power Rail
PMIC_INTnVDD_MCUIO_3V3
PMIC_nRSTOUTVDA_MCU_1V8
PMIC_nRSTOUT_SOCVDA_MCU_1V8
PMIC_I2C1VDD_MCUIO_3V3
PMIC_I2C2VDD_MCUIO_3V3

Please use Table 3-3 as a guide to understand GPIO assignments required for each PDN system feature. If the feature listed is not required, the digital connection can be removed; however, the GPIO pin is still configured per NVM defined default function shown. After the processor has booted up, the processor can reconfigure unused GPIOs to support new functions. Reconfiguration of the GPIO function is possible as long as that function is only needed after boot and default function does not cause any conflicts with normal operations (for example, two outputs driving same net).

Table 3-3 Digital Connections by System Feature
Device GPIO Mapping System Features(1)
PMIC Pin NVM Function PDN Signals Functional Safety Active SoC MCU - only MCU-Safety Island Retention
TPS65941319-Q1 nPWRON/ ENABLE Enable PMIC_ENABLE R R
INT INT PMIC_INTn R
nRSTOUT nRSTOUT PMIC_nRSTOUT R R R
SCL_I2C1 SCL_I2C1 PMIC_I2C1(2) R
SDA_I2C1 SDA_I2C1
GPIO_1 SCL_I2C2 PMIC_I2C2 R
GPIO_2 SDA_I2C2
GPIO_3 GPO EN_MCU3V3IO_LDSW R
GPIO_4 GPO EN_EXT_VDDR R O
GPIO_5 GPO EN_3V3IO_LDSW R
GPIO_6 GPO EN_1V8IO_LDSW R
GPIO_7 nERR_MCU PMIC_nERR_MCU R
GPIO_8 DISABLE_WDOG(3) PMIC_WKUP R
GPIO_9 GPI PMIC_nSLEEP
GPIO_10 GPI PMIC_CLK32OUT
GPIO_11 nRSTOUT_SOC PMIC_nRSTOUT_SoC R
(1) R is Required. O is optional. If left blank then the resource is not used to support the feature.
(2) I2C1 is the primary I2C communication and is required for functional safety. This communication channel is used to interrogate and clear interrupts as well as interface with the error signal monitor (ESM). The I2C is also used to transition between ACTIVE, MCU_ONLY, and RETENTION states. Alternatively, GPIO9, PMIC_nSLEEP is used to transition between states.
(3) If desired to disable the watchdog through hardware, GPIO_8 is required and must be set high by the time nRSTOUT goes high. After nRSTOUT is high, the watchdog state is latched and the pin can be configured for other functions through software.