SLVUCK7A november   2022  – july 2023 TPSF12C1 , TPSF12C1-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 EVM Description
    2. 2.2 Setup
      1. 2.2.1 High-Voltage Testing
      2. 2.2.2 EVM Connections
      3. 2.2.3 Low-Voltage Testing
    3. 2.3 Header Information
    4. 2.4 EVM Performance Validation
    5. 2.5 AEF Design Flow
      1. 2.5.1 AEF Circuit Optimization and Debug
  9. 3Implementation Results
    1. 3.1 EMI Performance
    2. 3.2 Thermal Performance
    3. 3.3 Surge Immunity
    4. 3.4 SENSE and INJ Voltages
    5. 3.5 Insertion Loss
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout
      1. 4.3.1 Assembly Drawings
      2. 4.3.2 Multi-Layer Stackup
  11. 5Compliance Information
    1. 5.1 Compliance and Certifications
  12. 6Additional Information
    1.     Trademarks
  13. 7Related Documentation
    1. 7.1 Supplemental Content
  14. 8Revision History

2.5 AEF Design Flow

Follow these steps to design an active filter circuit:

  1. Quickstart Calculator – Use the TPSF12C1 quickstart calculator as a convenient starting point. See Figure 3-5 for illustration.


    GUID-20230702-SS0I-NN32-GV7L-8MQQPTGMHD8X-low.svg Figure 2-5 Quickstart Calculator With CM Choke Impedance, Loop Gain and Insertion Loss Plots


    Typical steps to complete the quickstart calculator are as follows:
    • Choose the core material for the CM chokes – the primary choices being nanocrystalline (NC) or ferrite. NC chokes are preferable for active filter designs given their higher permeability (and thus fewer winding turns), broader impedance characteristic over frequency, more damped impedance behavior with softer phase transition, and better stability over temperature.
    • Define the CM choke impedances – two options are available:
      • Measure the CM impedance magnitude and phase vs. frequency using a network analyzer. Paste the data directly into the calculator file.
      • Enter the behavioral model parameters for each choke based on (a) a parallel LRC circuit for a ferrite choke (LCM || RPAR || CPAR), or (b) a ladder network for an NC choke consisting of three parallel RL circuits connected in series along with a parasitic capacitance across the total network. An equivalent circuit model is the most convenient option if the choke data sheet includes the CM impedance data.
    • Enter values for the grid-side and regulator-side Y-capacitors, sense capacitors and inject capacitor.
    • Enter values for source impedance of the grid supply and the noise source. Select from a drop-down menu if a LISN (50 µH or 5 µH) is installed.
    • Review the AEF loop gain plot for stability based on the calculated component values for the damping network. Adjust the damping network values to ensure the phase does not reach –180° at the resonant frequencies (when the gain is positive). Refer to the TPSF12C1 data sheet for guidance on component selection. Check the insertion loss plots with AEF enabled and disabled.


  2. Circuit Simulation – Avail of PSPICE or SIMPLIS simulation models for the TPSF12C1 device. Use such models along with prepared test benches to investigate the operation of the complete active filter circuit. See the SIMPLIS schematic in Figure 3-6 as an example. Perform both time-domain and frequency-domain analyses as required.
    GUID-20230716-SS0I-RD2F-XLMR-LMN8MMKWHSQX-low.svg Figure 2-6 SIMPLIS Simulation Schematic of an Active Filter Circuit Using the TPSF12C1

    Note that the CM choke model schematics are not shown above. If the choke model equivalent circuit parameters are defined in the quickstart calculator, transfer them directly to the simulation model as needed.


  3. Low-Voltage Tests – Validate the filter design at low voltage prior to connecting to the switching regulator. This is a relatively easy step to confirm various aspect of the design, including filter stability, insertion loss, voltage swing on the INJ pin, and EMI performance with CM signal excitation. See Figure 3-4 and refer to tests 4 through 7 described in Section 2.4.
    • Insertion loss – measure with 50-Ω source and load impedances.
    • Apply a CM excitation signal with a function generator.
      • Check the dynamic voltage range of the INJ pin (TPSF12C1 pin 13).
      • Measure the EMI (CM only, there is no DM propagation in this test).


  4. High-Voltage Tests – Validate the filter design while connected to the switching regulator. See Figure 3-3 and refer to tests 8 and 9 described in Section 2.4.
    • Check the dynamic voltage range of the INJ pin.
    • Calculate the device power dissipation(4) based on VVDD, IVDD, TA and RθJA. Verify that the maximum junction temperature is less than 150°C under the worst case operating conditions.
    • Check the sense and inject capacitance variation over temperature and ensure the circuit is stable under all operating conditions.
    • Measure the total EMI. Separate the CM (asymmetrical) and DM (symmetrical) propagation components, as the TPSF12C1-based AEF circuit only attenuates the CM noise.