SLVUCK7A november   2022  – july 2023 TPSF12C1 , TPSF12C1-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 EVM Description
    2. 2.2 Setup
      1. 2.2.1 High-Voltage Testing
      2. 2.2.2 EVM Connections
      3. 2.2.3 Low-Voltage Testing
    3. 2.3 Header Information
    4. 2.4 EVM Performance Validation
    5. 2.5 AEF Design Flow
      1. 2.5.1 AEF Circuit Optimization and Debug
  9. 3Implementation Results
    1. 3.1 EMI Performance
    2. 3.2 Thermal Performance
    3. 3.3 Surge Immunity
    4. 3.4 SENSE and INJ Voltages
    5. 3.5 Insertion Loss
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout
      1. 4.3.1 Assembly Drawings
      2. 4.3.2 Multi-Layer Stackup
  11. 5Compliance Information
    1. 5.1 Compliance and Certifications
  12. 6Additional Information
    1.     Trademarks
  13. 7Related Documentation
    1. 7.1 Supplemental Content
  14. 8Revision History

2.4 EVM Performance Validation

  1. Connect the EVM to the filter board (see receptacle J2 in Figure 3-3).
  2. Apply a VDD bias supply voltage of 8 V to 16 V (nominal 12 V, with ripple voltage less than 20 mV peak-to-peak) between the VDD and GND terminals of J1.
  3. Measure the voltage at the INJ pin of the TPSF12C1 (pin 13) with respect to GND; a DC voltage of VVDD/2 and have no AC perturbations that indicate instability. The VDD current consumption must be approximately 12 mA. If the INJ pin voltage is oscillating, modify the damping network components on the EVM to achieve stability.
  4. The user must perform low-voltage testing prior to connecting the high-voltage power stage. To provide a CM stimulus, connect a 5-V peak-to-peak square-wave source from a function generator as shown in Figure 3-4. Set the signal frequency to the switching freqeuncy of the power stage and choose a duty cycle that creates all the spectral harmonics (aside: 50% duty cycle eliminates the even harmonics, 33.3% removes the triple-n harmonics, and so forth). A 1-nF capacitor in series with the signal source emulates a practical CM noise source impedance.
    • Using this CM excitation source, verify the dynamic voltage range of the TPSF12C1 INJ pin. Ensure that the INJ pin voltage relative to GND operates in a window between 2.5 V and VVDD – 2 V.
  5. Connect a LISN on each input power line and measure the EMI with AEF disabled (EN tied to GND) to benchmark the existing passive filter. Short the low-voltage (bottom) terminal of the inject capacitor to GND when AEF is disabled by tying the INJ terminal on J1 to GND. This emulates the Y-capacitor connection in an equivalent passive filter design.
  6. Remove the pulldown short on the inject capacitor and enable the AEF circuit by allowing EN to float high. Repeat the EMI measurement, thus quantifying the EMI reduction with AEF.
  7. In a similar fashion, perform a comparison of filter insertion loss or attenuation performance using a network analyzer. For a true insertion loss measurement with 50-Ω source and load impedances, replace the LISN by a 50-Ω load tied from L or N to GND.
  8. Using high-voltage safety precautions, connect the switching power stage as shown in Figure 3-3. Turn the regulator ON and, similar to step 4, verify that the IC's INJ pin voltage is not getting clipped. To improve the dynamic range of the INJ voltage, increase one or more of the following:
    • Regulator-side Y-capacitance, CY3 and CY4
    • Inject capacitance, CINJ
    • VDD supply voltage, VVDD
  9. Measure the EMI with AEF enabled and disabled, similar to the procedure outlined in steps 5 and 6.
  10. Turn the regulator OFF. Wait for all high-voltage capacitors to fully discharge.