The D and A triggers, defined by the NSLEEP2 bit or pin, trigger the any2_s2r sequence to support the IO+DDR low power mode on the processor. This sequence disables all power rails except Buck4 and Buck5 which supplies the 1.8V IO domain and DDR rails.

The following PMIC PFSM instructions are executed automatically in the beginning and at the end of the power sequence:

//Instructions executed at the beginning of the sequence: 
//mask NSLEEP2 pin and NSLEEP2B bit
REG_WRITE_MASK_IMM ADDR=0x07D DATA=0x80 MASK=0x7F

// Instructions executed at the end of the sequence: 
// unmask NSLEEP2 pin and NSLEEP2B bit
REG_WRITE_MASK_IMM ADDR=0x07D DATA=0x00 MASK=0x7F
// set SPMI_LPM_EN
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF
// Clear AMUXOUT_EN, CLKMON_EN, set LPM_EN 
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xEB
REG_WRITE_MASK_IMM ADDR=0x081 DATA=0x04 MASK=0xE3