SLVUCM3 july   2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , TPS6593-Q1

 

  1.   1
  2.   User's Guide for Powering AM62A with TPS65931211-Q1 PMIC
  3.   Trademarks
  4. 1Introduction
  5. 2Device Versions
  6. 3Processor Connections
    1. 3.1 Power Mapping
      1. 3.1.1 Supporting 0.85V on VDD_CORE
      2. 3.1.2 Using 5V Input Supply
    2. 3.2 Control Mapping
  7. 4Supporting Functional Safety ASIL-B Requirements
  8. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Watchdog Settings
  9. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 Sequence: immediateOff2Safe_pd
      2. 6.3.2 Sequence: orderlyOff2safe
      3. 6.3.3 Sequence: warmReset
      4. 6.3.4 Sequence: any2active
      5. 6.3.5 Sequence: any2_s2r
  10. 7Application Examples
    1. 7.1 Entering and Exiting S2R (Suspend to RAM)
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
  11. 8References

6.3.3 Sequence: warmReset

The warmReset sequence can be triggered by either a watchdog, ESM_MCU or MCU_POWER_ERROR. An output failure detection on LDO2 is a valid condition for the MCU_POWER_ERROR trigger which executes a warm reset. An output failure on any of the remaining power resources (Buck1/2/3/4/5 and LDO1/3/4) executes an orderly shutdown. In the event of a warm reset trigger, the nRSTOUT is driven low and the recovery count (register RECOV_CNT_REG_1) increments. Then, all BUCKs and LDOs are reset to their default voltages. The PMICs remain in the ACTIVE state.

At the beginning of the sequence the following instructions are executed:

\\ Mask LDO1 UV/OV
REG_WRITE_MASK_IMM ADDR=0x04C DATA=0x03 MASK=0xFC
\\ Set SPMI_LPM_EN
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF
\\ Set LPM_EN and AMUXOUT_EN
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xEB
// Increment the recovery counter
REG_WRITE_MASK_IMM ADDR=0xa5 DATA=0x01 MASK=0xFE
Note: The watchdog or ESM error is an indication of a significant error which has taken place outside of the PMIC. The PMIC does not actually transition through the safe recovery, however, in order to maintain consistency all of the regulators are returned to the values stored in NVM and the recovery counter is incremented. If the recovery counter exceeds the recovery count threshold the PMICs stay in the safe recovery state. After the sequence, the MCU is responsible for managing the EN_DRV and recovery counter. At the end of the sequence the 'FORCE_EN_DRV_LOW' bit is cleared so that the MCU can set the ENABLE_DRV bit.

GUID-20230316-SS0I-WZCM-P3SG-LTC27ZBNXRJF-low.svg Figure 6-4 Warm reset Sequence