SLVUCM3 july   2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , TPS6593-Q1

 

  1.   1
  2.   User's Guide for Powering AM62A with TPS65931211-Q1 PMIC
  3.   Trademarks
  4. 1Introduction
  5. 2Device Versions
  6. 3Processor Connections
    1. 3.1 Power Mapping
      1. 3.1.1 Supporting 0.85V on VDD_CORE
      2. 3.1.2 Using 5V Input Supply
    2. 3.2 Control Mapping
  7. 4Supporting Functional Safety ASIL-B Requirements
  8. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Watchdog Settings
  9. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 Sequence: immediateOff2Safe_pd
      2. 6.3.2 Sequence: orderlyOff2safe
      3. 6.3.3 Sequence: warmReset
      4. 6.3.4 Sequence: any2active
      5. 6.3.5 Sequence: any2_s2r
  10. 7Application Examples
    1. 7.1 Entering and Exiting S2R (Suspend to RAM)
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
  11. 8References

6.3.2 Sequence: orderlyOff2safe

If a moderate error occurs, an orderly shutdown trigger is generated. This trigger shuts down the PMIC outputs using the recommended power down sequence and proceed to the TO_SAFE state.

If an OFF request occurs, such as the ENABLE pin of the TPS6593-Q1 device being pulled low, the same power down sequence occurs, except that the PMICs go to STANDBY (LP_STANDBY_SEL=0) or LP_STANDBY (LP_STANDBY_SEL=1) states, rather than going to the TO_SAFE state. The power sequence for both of these events is shown in Figure 6-3.

GUID-20230316-SS0I-RVCR-DTPX-KGFS5PRVXZVM-low.svg Figure 6-3 OrderlyOff Sequence