SLVUCM3 july   2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , TPS6593-Q1

 

  1.   1
  2.   User's Guide for Powering AM62A with TPS65931211-Q1 PMIC
  3.   Trademarks
  4. 1Introduction
  5. 2Device Versions
  6. 3Processor Connections
    1. 3.1 Power Mapping
      1. 3.1.1 Supporting 0.85V on VDD_CORE
      2. 3.1.2 Using 5V Input Supply
    2. 3.2 Control Mapping
  7. 4Supporting Functional Safety ASIL-B Requirements
  8. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Watchdog Settings
  9. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 Sequence: immediateOff2Safe_pd
      2. 6.3.2 Sequence: orderlyOff2safe
      3. 6.3.3 Sequence: warmReset
      4. 6.3.4 Sequence: any2active
      5. 6.3.5 Sequence: any2_s2r
  10. 7Application Examples
    1. 7.1 Entering and Exiting S2R (Suspend to RAM)
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
  11. 8References

4 Supporting Functional Safety ASIL-B Requirements

To achieve a system functional safety level of ASIL-B, the following PDN features are available:

  • PMIC over voltage and under voltage monitoring on the power resource voltage outputs
  • Watchdog monitoring of safety processor
  • MCU error monitoring
  • MCU and Main Domain cold reset
  • I2C communication
  • Error indicator, EN_DRV, for driving external circuitry (optional)
  • Read-back of EN_DRV pin

Additional Safety Features

  • PMIC current monitoring on all output power rails
  • Switch short-to-ground detection on BUCK regulator pins (SW_Bx)
  • Read-back of nINT and nRSTOUT logic output pins

The PMIC internal over voltage and under voltage monitoring and their respective monitoring threshold levels are enabled by default and can be updated through I2C after startup. PMIC power rails connected directly to the processor are monitored by default. The unused feedback pin of BUCK3 on TPS65931211-Q1, FB_B3, is assigned to monitor the load switch output voltage that supplies the 3.3V I/O domain. A 3.3V supply must be connected to the feedback pin in order to prevent an error since the PMIC is expecting the 3.3V to be present.

The internal Q&A Watchdog is enabled on the TPS65931211-Q1 NVM. Once the device is in ACTIVE state, the trigger or Q&A watchdog settings can be configured through the secondary I2C2 (GPIO1/GPIO2) in the device. The primary and secondary I2C CRC is not enabled by default but must be enabled with the I2C_2 trigger described in Section 6.2. Once enabled the secondary I2C is disabled for 2ms. It is recommended to enable I2C CRC and wait a minimum of 2ms before starting the Q&A Watchdog. The steps for configuring and starting the watchdog can be found in the TPS6593-Q1 data sheet. Setting the DISABLE_WDOG signal high disables the watchdog timer if this feature needs to be suspended during initial development or is not required in the system.

GPIO_7 of the primary TPS65931211-Q1 PMIC is configured as the MCU error signal monitor, and must be enabled though the ESM_MCU_EN register bit. MCU and Main Domain reset is supported through the connection between the nRSTOUT pin of the PMIC and the MCU_PORz pin of the processor.

There is an option to use the EN_DRV to indicate an error has been detected and the system is entering SAFE state. This signal can be utilized if the system has external circuitry that needs to be driven by an error event. In this PDN, the EN_DRV is not utilized, but available if needed.

The current monitoring is enabled by default for all BUCKs and LDOs.

Table 4-1 PMIC System Level Safety Features
ASIL-B
External SW Wdog INTn

Safety MCU Processing ESM

Safety MCU Reset

 Safety Status Signal with IO Read-Back feature System Input Voltage Monitoring
PMIC: Q&A Watchdog and I2C2.

PMIC: nINT pin connected to EXTINTn on the processor

PMIC: nERR_MCU connected to MCU_ERRORn on the processor

PMIC: ENDRV VCCA OV/UV is disabled by default but can be enabled by I2C.
Table 4-2 PMIC Power Monitoring Safety Features
Device Power Resource PDN Power Rail ASIL-B

Supply Voltage Monitoring
TPS65931211-Q1 (PMIC) BUCK1-3 VDD_CORE PMIC - OV & UV
BUCK4 VDDS_DDR PMIC - OV & UV
BUCK5 DVDD1V8(VDDSHVy) PMIC - OV & UV
LDO1 VDDSHV5 PMIC - OV & UV

check with mike if UV/OV are monitored when LDO is configured as bypass
LDO2 VPP (eFUSE) PMIC - OV & UV
LDO3 VDDR_CORE PMIC - OV & UV
LDO4 VDDA_MCU PMIC - OV & UV
TPS22965-Q1 Load Switch DVDD3V3(VDDSHVx) PMIC (FB_B3) - OV & UV

Note: Refer to the Safety Manual of the TPS6593-Q1 device for full descriptions and analysis of the PMIC functional safety features. These functional safety features can assist in achieving up to ASIL-B rating for a system.