SLVUCM3 july   2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , TPS6593-Q1

 

  1.   1
  2.   User's Guide for Powering AM62A with TPS65931211-Q1 PMIC
  3.   Trademarks
  4. 1Introduction
  5. 2Device Versions
  6. 3Processor Connections
    1. 3.1 Power Mapping
      1. 3.1.1 Supporting 0.85V on VDD_CORE
      2. 3.1.2 Using 5V Input Supply
    2. 3.2 Control Mapping
  7. 4Supporting Functional Safety ASIL-B Requirements
  8. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Watchdog Settings
  9. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 Sequence: immediateOff2Safe_pd
      2. 6.3.2 Sequence: orderlyOff2safe
      3. 6.3.3 Sequence: warmReset
      4. 6.3.4 Sequence: any2active
      5. 6.3.5 Sequence: any2_s2r
  10. 7Application Examples
    1. 7.1 Entering and Exiting S2R (Suspend to RAM)
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
  11. 8References

5.4 LDO Settings

These settings detail the voltages, configurations, and monitoring of the LDO rails stored in the NVM. All these settings can be changed though I2C after startup. Some settings, typically the enable bits, are also changed by the PFSM, as described in Section 6.3.

After the Section 6.3.4 sequence has completed, the LDOx_EN and LDOx_VMON_EN bits are set and the LDOx_RV_SEL bit is cleared for all LDOs. The other bits remain unchanged, but are still accessible via I2C.

Table 5-4 LDO NVM Settings
Register Name Field Name TPS65931211-Q1
Value Description
LDO1_CTRL LDO1_EN 0x0 Disabled; LDO1 regulator.
LDO1_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET
LDO1_PLDN 0x1 125 Ohm
LDO1_VMON_EN 0x0 Disable OV and UV comparators.
LDO1_RV_SEL 0x0 Disabled
LDO2_CTRL LDO2_EN 0x0 Disabled; LDO2 regulator.
LDO2_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET
LDO2_PLDN 0x0 50 kOhm
LDO2_VMON_EN 0x0 Disabled; OV and UV comparators.
LDO2_RV_SEL 0x0 Disabled
LDO3_CTRL LDO3_EN 0x0 Disabled; LDO3 regulator.
LDO3_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET
LDO3_PLDN 0x1 125 Ohm
LDO3_VMON_EN 0x0 Disabled; OV and UV comparators.
LDO3_RV_SEL 0x0 Disabled
LDO4_CTRL LDO4_EN 0x0 Disabled; LDO4 regulator.
LDO4_SLOW_RAMP 0x1 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET
LDO4_PLDN 0x1 125 Ohm
LDO4_VMON_EN 0x0 Disabled; OV and UV comparators.
LDO4_RV_SEL 0x0 Disabled
LDO1_VOUT LDO1_VSET 0x3a 3.30 V
LDO1_BYPASS 0x1 Bypass mode.
LDO2_VOUT LDO2_VSET 0x1c 1.80 V
LDO2_BYPASS 0x0 Linear regulator mode.
LDO3_VOUT LDO3_VSET 0x9 0.85 V
LDO3_BYPASS 0x0 Linear regulator mode.
LDO4_VOUT LDO4_VSET 0x38 1.800 V
LDO1_PG_WINDOW LDO1_OV_THR 0x4 +6% / +60 mV
LDO1_UV_THR 0x4 -6% / -60 mV
LDO2_PG_WINDOW LDO2_OV_THR 0x4 +6% / +60 mV
LDO2_UV_THR 0x4 -6% / -60 mV
LDO3_PG_WINDOW LDO3_OV_THR 0x4 +6% / +60 mV
LDO3_UV_THR 0x4 -6% / -60 mV
LDO4_PG_WINDOW LDO4_OV_THR 0x4 +6% / +60 mV
LDO4_UV_THR 0x4 -6% / -60 mV