SLVUCM3 july   2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , TPS6593-Q1

 

  1.   1
  2.   User's Guide for Powering AM62A with TPS65931211-Q1 PMIC
  3.   Trademarks
  4. 1Introduction
  5. 2Device Versions
  6. 3Processor Connections
    1. 3.1 Power Mapping
      1. 3.1.1 Supporting 0.85V on VDD_CORE
      2. 3.1.2 Using 5V Input Supply
    2. 3.2 Control Mapping
  7. 4Supporting Functional Safety ASIL-B Requirements
  8. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Watchdog Settings
  9. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 Sequence: immediateOff2Safe_pd
      2. 6.3.2 Sequence: orderlyOff2safe
      3. 6.3.3 Sequence: warmReset
      4. 6.3.4 Sequence: any2active
      5. 6.3.5 Sequence: any2_s2r
  10. 7Application Examples
    1. 7.1 Entering and Exiting S2R (Suspend to RAM)
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
  11. 8References

3.1.2 Using 5V Input Supply

The PDN described in this user's guide was designed for 3.3V input supply. However the TPS65931211-Q1 NVM also supports 5V input supply. The default NVM settings on TPS65931211-Q1 have the UV/OV disabled on VCCA so PMIC can use either voltage (3.3V or 5V). If 5V supply is used, then a 3.3V discrete Buck is required for the 3.3V IO domain instead of a power switch. The external 3.3V Buck can be enabled by GPIO4 and needs to ramp from 0V to 3.3V within the 10ms delay that was assigned to GPIO4 in the any2active sequence.

LDO1 is configured as “bypass” and requires a 3.3V supply. This LDO can be supplied by the output of the discrete 3.3V regulator. TI also recommends supplying the remaining LDOs (LDO3 and LDO4) with the discrete 3.3V regulator to reduce power dissipation. VIO_IN must be supplied by 3.3V as well.

When using 5V instead of 3.3V, the voltage from the pre-regulator cannot be directly connected to VDDSHV_CANUART. In this case, VDDSHV_CANUART can be supplied by the same discrete 3.3 V Buck that supplies the remaining 3.3 V signals on the processor.