SLVUCR7 September   2024 TPS26750

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     National Conventions
    3.     Glossary
    4.     Related Documents
    5.     Support Resources
    6.     Trademarks
  3. 1Introduction
    1. 1.1 Introduction
      1. 1.1.1 Purpose and Scope
    2. 1.2 PD Controller Host Interface Description
      1. 1.2.1 Overview
      2. 1.2.2 Register and field notation
    3. 1.3 Unique Address Interface
      1. 1.3.1 Unique Address Interface Protocol
  4. 2PD Controller Policy Modes
    1. 2.1 Overview
    2. 2.2 Source Policy Mode
    3. 2.3 Sink Policy Mode
  5. 3Register Overview
  6. 4TPS26750 Registers
  7. 54CC Task Detailed Descriptions
    1. 5.1 Overview
    2. 5.2 CPU Control Tasks
      1. 5.2.1 'Gaid' - Return to normal operation
      2. 5.2.2 'GAID' - Cold reset request
    3. 5.3 PD Message Tasks
      1. 5.3.1  'SWSk' - PD PR_Swap to Sink
      2. 5.3.2  'SWSr' - PD PR_Swap to Source
      3. 5.3.3  'SWDF' - PD DR_Swap to DFP
      4. 5.3.4  'SWUF' - PD DR_Swap to UFP
      5. 5.3.5  'GSkC' - PD Get Sink Capabilities
      6. 5.3.6  'GSrC' - PD Get Source Capabilities
      7. 5.3.7  'ESkC' - PD EPR Get Sink Capabilities
      8. 5.3.8  'ESrC' - PD EPR Get Source Capabilities
      9. 5.3.9  'GPPI' - PD Get Port Partner Information
      10. 5.3.10 'SSrC' - PD Send Source Capabilities
      11. 5.3.11 'MBRd' - Message Buffer Read
    4. 5.4 Patch Bundle Update Tasks
      1. 5.4.1 'PBMs' - Start Patch Burst Mode Download Sequence
      2. 5.4.2 'PBMc' - Patch Burst Mode Download Complete
      3. 5.4.3 'PBMe' - End Patch Burst Mode Download Sequence
      4. 5.4.4 'GO2P' - Go to Patch Mode
      5. 5.4.5 'FLrd' - Flash Memory Read
      6. 5.4.6 'FLad' - Flash Memory Write Start Address
      7. 5.4.7 'FLwd' - Flash Memory Write
      8. 5.4.8 'FLvy' - Flash Memory Verify
    5. 5.5 System Tasks
      1. 5.5.1 'DBfg' - Clear Dead Battery Flag
      2. 5.5.2 'I2Cr' - I2C read transaction
      3. 5.5.3 'I2Cw' - I2C write transaction
      4. 5.5.4 'GPsh' - set GPIO high
      5. 5.5.5 'GPsl' - set GPIO low
  8. 6User Reference
    1. 6.1 PD Controller Application Customization
    2. 6.2 Loading a Patch Bundle
    3. 6.3 AUTO_NEGOTIATE_SINK Register
      1. 6.3.1 AUTO_NEGOTIATE_SINK usage example #1
      2. 6.3.2 AUTO_NEGOTIATE_SINK usage example #2
      3. 6.3.3 AUTO_NEGOTIATE_SINK usage example #3
      4. 6.3.4 AUTO_NEGOTIATE_SINK usage example #4
    4. 6.4 IO_CONFIG Register
      1. 6.4.1 GPIO Events
  9. 7Revision History

6.2 Loading a Patch Bundle

The patch bundle can contain Application Customization data and a Patch binary that modifies the default application firmware in the PD controller. This section will describe how the host can load the patch bundle. The host uses the I2Ct bus for all transactions related to loading the patch bundle. As noted in the flow diagram below, the I2C target address varies depending upon which mode the PD controller is in. The Patch Burst Mode allows the host to push the Patch Bundle to multiple PD controllers simultaneously.

The following flow diagram illustrates the normal successful patch loading process. Other error handling steps can be necessary depending upon the nature of the errors encountered for a particular system. The EC can reset and restart the patch process by issuing a 'PBMe' 4CC Task.

Table 6-1 Use of Target Addresses During Different Modes of Operation
MODE Register Read-Back Value I2Ct
Target Address 1
'BOOT' As configured by ADCINx pins. This is the "Fundamental" I2C target address. BOOT indicates that the PD controller is in the boot stage due to a bad firmware image or incorrect ADCINx settings. APP indicates that the firmware has successfully loaded and is in normal operation. PTCH indicates that the PD controller is waiting for a patch or is in the patch process using the PBMx commands.
'PTCH'(1)
'APP '(2)
(1) A successful 'PBMs' Task puts the PD controller into the 'PTCH' mode.
(2) A successful 'PBMc' Task puts the PD controller into the 'APP ' mode.
Flow for Pushing a Patch Bundle Over the I2Ct Bus to Multiple PD Controllers at the Same Time Figure 6-1 Flow for Pushing a Patch Bundle Over the I2Ct Bus to Multiple PD Controllers at the Same Time

While the host is writing the Patch Bundle burst data, the I2C protocol in the following figure must be followed. The host can send the entire Patch Bundle in a single I2C transaction, or it can break it up into multiple transactions. The PD controller increments the pointer into its patch memory space with each byte received on the Patch Target address that was configured by DATA1.TargetAddress as part of the 'PBMs' 4CC Task. The EC can re-issue a 'PBMs' 4CC Task or it can issue a 'PBMe' 4CC Task in order to reset the pointer.

Protocol of Patch Bundle Burst Data Assuming it is Broken Into Two Transactions Figure 6-2 Protocol of Patch Bundle Burst Data Assuming it is Broken Into Two Transactions