SLVUCR7 September   2024 TPS26750

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     National Conventions
    3.     Glossary
    4.     Related Documents
    5.     Support Resources
    6.     Trademarks
  3. 1Introduction
    1. 1.1 Introduction
      1. 1.1.1 Purpose and Scope
    2. 1.2 PD Controller Host Interface Description
      1. 1.2.1 Overview
      2. 1.2.2 Register and field notation
    3. 1.3 Unique Address Interface
      1. 1.3.1 Unique Address Interface Protocol
  4. 2PD Controller Policy Modes
    1. 2.1 Overview
    2. 2.2 Source Policy Mode
    3. 2.3 Sink Policy Mode
  5. 3Register Overview
  6. 4TPS26750 Registers
  7. 54CC Task Detailed Descriptions
    1. 5.1 Overview
    2. 5.2 CPU Control Tasks
      1. 5.2.1 'Gaid' - Return to normal operation
      2. 5.2.2 'GAID' - Cold reset request
    3. 5.3 PD Message Tasks
      1. 5.3.1  'SWSk' - PD PR_Swap to Sink
      2. 5.3.2  'SWSr' - PD PR_Swap to Source
      3. 5.3.3  'SWDF' - PD DR_Swap to DFP
      4. 5.3.4  'SWUF' - PD DR_Swap to UFP
      5. 5.3.5  'GSkC' - PD Get Sink Capabilities
      6. 5.3.6  'GSrC' - PD Get Source Capabilities
      7. 5.3.7  'ESkC' - PD EPR Get Sink Capabilities
      8. 5.3.8  'ESrC' - PD EPR Get Source Capabilities
      9. 5.3.9  'GPPI' - PD Get Port Partner Information
      10. 5.3.10 'SSrC' - PD Send Source Capabilities
      11. 5.3.11 'MBRd' - Message Buffer Read
    4. 5.4 Patch Bundle Update Tasks
      1. 5.4.1 'PBMs' - Start Patch Burst Mode Download Sequence
      2. 5.4.2 'PBMc' - Patch Burst Mode Download Complete
      3. 5.4.3 'PBMe' - End Patch Burst Mode Download Sequence
      4. 5.4.4 'GO2P' - Go to Patch Mode
      5. 5.4.5 'FLrd' - Flash Memory Read
      6. 5.4.6 'FLad' - Flash Memory Write Start Address
      7. 5.4.7 'FLwd' - Flash Memory Write
      8. 5.4.8 'FLvy' - Flash Memory Verify
    5. 5.5 System Tasks
      1. 5.5.1 'DBfg' - Clear Dead Battery Flag
      2. 5.5.2 'I2Cr' - I2C read transaction
      3. 5.5.3 'I2Cw' - I2C write transaction
      4. 5.5.4 'GPsh' - set GPIO high
      5. 5.5.5 'GPsl' - set GPIO low
  8. 6User Reference
    1. 6.1 PD Controller Application Customization
    2. 6.2 Loading a Patch Bundle
    3. 6.3 AUTO_NEGOTIATE_SINK Register
      1. 6.3.1 AUTO_NEGOTIATE_SINK usage example #1
      2. 6.3.2 AUTO_NEGOTIATE_SINK usage example #2
      3. 6.3.3 AUTO_NEGOTIATE_SINK usage example #3
      4. 6.3.4 AUTO_NEGOTIATE_SINK usage example #4
    4. 6.4 IO_CONFIG Register
      1. 6.4.1 GPIO Events
  9. 7Revision History

6.4 IO_CONFIG Register

The figure below shows the interface for the GPIO hardware. The register fields GPIO_AI_EN, GPIO_PD_EN, GPIO_PU_EN, GPIO_OE, and GPIO_OD_EN listed in the table below are passed along to the GPIO hardware, independent of the GPIO Event that is configured. The PD controller will then set the signal GPIO_O to high or low to implement the selected output GPIO event. So for example, each output GPIO Event is configurable as push-pull or open-drain using the GPIO_OD_EN bit. For input GPIO events the PD controller will monitor GPIO_I from the figure.

A given GPIO Event can only be assigned to one GPIO pin.

The ProcHot_N_Event GPIO Event can be assigned to any GPIO, but for some PD controllers only a specific GPIO will have the fast reaction time feature (see device data-sheet).

Interface to GPIO hardwareFigure 6-3 Interface to GPIO hardware.