SLVUCR7 September   2024 TPS26750

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     National Conventions
    3.     Glossary
    4.     Related Documents
    5.     Support Resources
    6.     Trademarks
  3. 1Introduction
    1. 1.1 Introduction
      1. 1.1.1 Purpose and Scope
    2. 1.2 PD Controller Host Interface Description
      1. 1.2.1 Overview
      2. 1.2.2 Register and field notation
    3. 1.3 Unique Address Interface
      1. 1.3.1 Unique Address Interface Protocol
  4. 2PD Controller Policy Modes
    1. 2.1 Overview
    2. 2.2 Source Policy Mode
    3. 2.3 Sink Policy Mode
  5. 3Register Overview
  6. 4TPS26750 Registers
  7. 54CC Task Detailed Descriptions
    1. 5.1 Overview
    2. 5.2 CPU Control Tasks
      1. 5.2.1 'Gaid' - Return to normal operation
      2. 5.2.2 'GAID' - Cold reset request
    3. 5.3 PD Message Tasks
      1. 5.3.1  'SWSk' - PD PR_Swap to Sink
      2. 5.3.2  'SWSr' - PD PR_Swap to Source
      3. 5.3.3  'SWDF' - PD DR_Swap to DFP
      4. 5.3.4  'SWUF' - PD DR_Swap to UFP
      5. 5.3.5  'GSkC' - PD Get Sink Capabilities
      6. 5.3.6  'GSrC' - PD Get Source Capabilities
      7. 5.3.7  'ESkC' - PD EPR Get Sink Capabilities
      8. 5.3.8  'ESrC' - PD EPR Get Source Capabilities
      9. 5.3.9  'GPPI' - PD Get Port Partner Information
      10. 5.3.10 'SSrC' - PD Send Source Capabilities
      11. 5.3.11 'MBRd' - Message Buffer Read
    4. 5.4 Patch Bundle Update Tasks
      1. 5.4.1 'PBMs' - Start Patch Burst Mode Download Sequence
      2. 5.4.2 'PBMc' - Patch Burst Mode Download Complete
      3. 5.4.3 'PBMe' - End Patch Burst Mode Download Sequence
      4. 5.4.4 'GO2P' - Go to Patch Mode
      5. 5.4.5 'FLrd' - Flash Memory Read
      6. 5.4.6 'FLad' - Flash Memory Write Start Address
      7. 5.4.7 'FLwd' - Flash Memory Write
      8. 5.4.8 'FLvy' - Flash Memory Verify
    5. 5.5 System Tasks
      1. 5.5.1 'DBfg' - Clear Dead Battery Flag
      2. 5.5.2 'I2Cr' - I2C read transaction
      3. 5.5.3 'I2Cw' - I2C write transaction
      4. 5.5.4 'GPsh' - set GPIO high
      5. 5.5.5 'GPsl' - set GPIO low
  8. 6User Reference
    1. 6.1 PD Controller Application Customization
    2. 6.2 Loading a Patch Bundle
    3. 6.3 AUTO_NEGOTIATE_SINK Register
      1. 6.3.1 AUTO_NEGOTIATE_SINK usage example #1
      2. 6.3.2 AUTO_NEGOTIATE_SINK usage example #2
      3. 6.3.3 AUTO_NEGOTIATE_SINK usage example #3
      4. 6.3.4 AUTO_NEGOTIATE_SINK usage example #4
    4. 6.4 IO_CONFIG Register
      1. 6.4.1 GPIO Events
  9. 7Revision History

6.4.1 GPIO Events

Table 6-6 GPIO Events
Event #Event NameI/ODescription
158 WAIT_nPG Input GPIO from battery charger to indicate to the PD controller can communicate over I2C during a dead battery power up condition.
157 LIQUID_DETECTED Output GPIO is asserted when liquid is detected on the SBU1/2 pins. When liquid is no longer detected on the SBU1/2 pins the GPIO will be de-asserted.
156 LIQUID_NMOS_CONTROL Output GPIO used to enable the NMOS in the external liquid detection circuit. The GPIO will toggle during liquid detection.
155 LIQUID_PMOS_CONTROL Output GPIO used to enable the PMOS in the external liquid detection circuit. The GPIO will toggle during liquid detection.
142 EPR_DISCHARGE_EVENT Output GPIO is enabled when there is a disconnect or a negative voltage tranistion in EPR mode. This GPIO drives an external discharge circuit.
92 VBUS_SENSE_DIVIDER Output GPIO is enable whenever the PD controller is transitioning into EPR mode. This GPIO will enable the external VBUS divider to keep the voltage range within the tolerance of the PD controller.
76PdNegotiationInProcessOutput

When in source mode, this GPIO is asserted after a Request message is received, before sending the Accept message. The GPIO is de-asserted after the PS_RDY message is sent.

When in sink mode, this GPIO is asserted right before sending a Request message, and de-asserted after a PS_RDY message is received.

In either mode, the GPIO is de-asserted when a detach occurs.

75AttachedAsSinkOutputWhen the PD controller has a port that is connected to a Source, this GPIO will be asserted. The GPIO is de-asserted upon disconnect, hard reset, during power-role swap and during fast-role swap only if none of the ports in the PD controller are connected to a source.
73EnableSource_Port1OutputPD controller will assert this GPIO when acting as a source (implicit or explicit contract)
65Load_Switch_Drive_Port1OutputWhen the PD controller enables the PP_EXT1 sinking path, it will pull the selected GPIO low to enable a load-switch. When the PD controller disables the PP_EXT1 sinking path, it will drive the selected GPIO high.
61Dp_Dm_Mux_Enable_Event_Port1OutputThis GPIO must be used to enable/disable a USB 2.0 D+/D- mux. The GPIO is driven high upon connection, and low upon disconnect on Port1.
50Debug_Accessory_Mode_Event_Port1OutputOutput: This GPIO is asserted high when a Debug Accessory is attached on Port1.
45Prevent_DRSwap_To_UFP_EventInputWhen the GPIO is high, the PD controller will reject any DR_Swap messages from the Port Partner requesting to change the data-role from DFP to UFP.
44UFP_Indicator_EventOutputThe GPIO is driven high when the data role of any port in the PD controller is UFP.
43Barrel_Jack_EventInputWhen this GPIO is high, the PD controller interprets it to mean that a barrel-jack adaptor is connected and the system has Unconstrained power. A falling edge on this GPIO will automatically set PORT_CONTROL.UnconstrainedPower to 0 and TX_SCEDB.SourceInputs[0] to 0. A rising edge on this GPIO will automatically set PORT_CONTROL.UnconstrainedPower to 1 and TX_SCEDB.SourceInputs[0] to 1.
35Fault_Condition_Active_Low_Event_Port1OutputAsserts low on an overcurrent event on Port1.
33Fault_Input_Event_Port1InputWhen set low by the system, Port1 enters the Type-C Error Recovery State. When set high, no action is taken.
29UFP_DFP_Event_Port1OutputOutput: Asserted high when Port1 is operating as UFP. Asserted low when port is operating as DFP.
13SourcePDOContractBit2_Port1OutputOutput: Bit2 of binary encoded outputs indicating when a Source PDO1 through PDO7 on Port1 has been negotiated (the Accept message has been transmitted and the tSrcTransition timer has expired).
12SourcePDOContractBit1_Port1OutputOutput: Bit1 of binary encoded outputs indicating when a Source PDO1 through PDO7 on Port1 has been negotiated (the Accept message has been transmitted and the tSrcTransition timer has expired).
11SourcePDOContractBit0_Port1OutputOutput: Bit0 of binary encoded outputs indicating when a Source PDO1 through PDO7 on Port1 has been negotiated (the Accept message has been transmitted and the tSrcTransition timer has expired).
10SourcePDO4Contract_Port1OutputOutput: Asserted high when a Source PDO4 on Port1 has been negotiated (the Accept message has been transmitted and the tSrcTransition timer has expired). D-asserted when a PDO other than PDO2 has been negotiated.
9SourcePDO3Contract_Port1OutputOutput: Asserted high when a Source PDO3 on Port1 has been negotiated (the Accept message has been transmitted and the tSrcTransition timer has expired). D-asserted when a PDO other than PDO2 has been negotiated.
8SourcePDO2Contract_Port1OutputOutput: Asserted high when a Source PDO2 on Port1 has been negotiated (the Accept message has been transmitted and the tSrcTransition timer has expired). D-asserted when a PDO other than PDO2 has been negotiated.
7SourcePDO1Contract_Port1OutputOutput: Asserted high when a Source PDO1 on Port1 has been negotiated (the Accept message has been transmitted and the tSrcTransition timer has expired). D-asserted when a PDO other than PDO1 has been negotiated.
3Cable_Orientation_Event_Port1OutputOutput: Indicates the plug orientation on Port1. Low when the plug is connected upside-up (CC1 connected to CC in cable) or disconnected. High when plug is connected upside-down (CC2 connected to CC in cable).
1PlugEvent_Port1OutputOutput: Asserted high when plug event (attached state) has occurred on Port1, otherwise low.
0NullEventNANo event associated with this GPIO.