SLVUCX1 September   2024 TPS548B23

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Configurations and Modifications
      1. 2.1.1 Multifunction Configuration (CFG1-5) Pins Selection
      2. 2.1.2 Setting Output Voltage Using External Feedback Configuration
  9. 3Implementation Results
    1. 3.1 Test Setup and Results
      1. 3.1.1 Input and Output Connections
      2. 3.1.2 Efficiency
      3. 3.1.3 Output Voltage Regulation
      4. 3.1.4 Load Transient and Loop Response
      5. 3.1.5 Output Voltage Ripple
      6. 3.1.6 Start-up and Shutdown with EN
      7. 3.1.7 Thermal Performance
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 Board Layout
      1. 4.2.1 Layout
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1. 5.1 Trademarks

2.1.1 Multifunction Configuration (CFG1-5) Pins Selection

The multifunction configuration pins (CFG1-5) allow the device to be configured for various operating modes. The CFG1-2 pins set the device switching frequency, overcurrent threshold, soft start time, and either hiccup or latch-up fault recovery operation, while the CFG3-5 pins provide selectability for internal or external feedback as well as FCCM or PFM operation.

When the device is configured for internal feedback operation with the CFG 3-5 pins (see Table 2-3), the switching frequency and current limit are programmed by tying the CFG1-2 pins either high (VCC), low (GND) or left floating based on Table 2-1.

Note: When the device is configured for internal feedback operation, the soft start time is set to 2ms, and the fault recovery is configured for hiccup.

Table 2-1 CFG1-2 Pin Jumper (JP3-4) Selection for Internal Feedback Configuration
JP3 (CFG1) JP4 (CFG2) SWITCHING FREQUENCY (fSW) (kHz) Valley OCP (A)
VCC VCC 600 21
VCC(1) GND(1) 800 21
VCC Float 1200 21
GND VCC 600 18
GND GND 800 18
GND Float 1200 18
Float VCC 600 15
Float GND 800 15
Float Float 1200 15
(1) Default jumper setting

When the device is configured for external feedback operation with the CFG 3-5 pins, the switching frequency, fault recovery mode, overcurrent threshold, and soft start time are programmed by connecting resistors between the CFG1-2 pins and AGND (see Table 2-3). The switching frequency, fault recovery mode, and soft start time are programmed by connecting a resistor (R6) between the CFG1 pin and AGND based on Table 2-2.

Note: For external feedback operation, remove jumpers JP3 and JP4 and install R6 and R7.
Table 2-2 CFG1 Pin Resistor (R6) Selection for External Feedback Configuration
R6 (CFG1 PIN RESISTANCE TO AGND)(kΩ) SWITCHING FREQUENCY (fSW) (kHz) FAULT RECOVERY MODE SOFT START TIME (ms)
0 (GND) 600 Hiccup 1
4.99 800 Hiccup 1
7.50 1000 Hiccup 1
10.5 1200 Hiccup 1
13.3 600 Latch Off 1
16.9 800 Latch Off 1
21.0 1000 Latch Off 1
24.9 1200 Latch Off 1
30.1 600 Hiccup 2
35.7 800 Hiccup 2
42.2 1000 Hiccup 2
48.7 1200 Hiccup 2
56.2 600 Latch Off 2
64.9 800 Latch Off 2
75.0 1000 Latch Off 2
86.6 1200 Latch Off 2
102 600 Hiccup 3
118 800 Hiccup 3
137 1000 Hiccup 3
158 1200 Hiccup 3
182 600 Latch Off 3
210 800 Latch Off 3
243 1000 Latch Off 3
≥280 (Float) 1200 Latch Off 3

The valley overcurrent protection is programmed with a resistor (R7) between CFG2 and AGND based on Equation 1:

Equation 1. R7 = K O C L I O C L I M - 1 2 × V I N - V O × V O V I N × 1 L × f S W

where

  • IOCLIM is overcurrent limit threshold for load current in A
  • R7 is ILIM resistor value in Ω
  • KOCL is a constant of 84×103 for the calculation
  • VIN is input voltage value in V
  • VO is output voltage value in V
  • L is output inductor value in µH
  • fSW is switching frequency in MHz
Equation 2. I O C L I M = K O C L R7 + 1 2 × V I N - V O × V O V I N × 1 L × f S W
Note: TI recommends a ±1% tolerance resistor because a worse tolerance resistor provides less accurate OCL threshold.

To protect the device from an unexpected connection to the ILIM pin, an internal fixed OCL clamp is implemented. This internal OCL clamp limits the maximum valley current on the low-side MOSFET to 21A when the ILIM pin has too small of a resistance to AGND, or is accidentally shorted to ground.

The CFG3-5 pins select the device output voltage configuration as well as FCCM or PFM operation based on Table 2-3.

Table 2-3 CFG3-5 Pin Jumper (JP5-7) Selections
JP5 (CFG3) JP6 (CFG4) JP7 (CFG5) VFB Config VOUT(V) FSW Mode
VCC VCC VCC internal 5.0 FCCM
VCC GND VCC internal 3.3 FCCM
VCC Float VCC internal 2.5 FCCM
VCC VCC GND internal 1.8 FCCM
VCC GND GND internal 1.5 FCCM
VCC Float GND internal 1.2 FCCM
VCC VCC Float internal 1.1 FCCM
VCC GND Float internal 1.05 FCCM
VCC(1) Float(1) Float(1) internal 1.0 FCCM
GND VCC VCC internal 0.95 FCCM
GND GND VCC internal 0.9 FCCM
GND Float VCC internal 0.85 FCCM
GND VCC GND internal 0.8 FCCM
GND GND GND external 0.5 FCCM
GND Float GND internal 5.0 PFM
GND VCC Float internal 3.3 PFM
GND GND Float internal 2.5 PFM
GND Float Float internal 1.8 PFM
Float VCC VCC internal 1.5 PFM
Float GND VCC internal 1.2 PFM
Float Float VCC internal 1.1 PFM
Float VCC GND internal 1.0 PFM
Float GND GND internal 0.95 PFM
Float Float GND internal 0.9 PFM
Float VCC Float internal 0.85 PFM
Float GND Float internal 0.8 PFM
Float Float Float external 0.5 PFM
(1) Default jumper setting