SLVUCX1 September 2024 TPS548B23
The efficiency on the TPS548B23EVM is shown in Figure 3-1 and Figure 3-2. The test points used for the efficiency measurement are listed in Table 3-4. Use these test points to minimize the contribution of PCB parasitic power loss to the measured power loss.
The following are some additional test setup considerations to minimize external sources of power dissipation.
TEST POINT NAME | REFERENCE DESIGNATOR | FUNCTION |
---|---|---|
VIN_S | TP1 | Input voltage test point connected near pins |
PGND_S | TP18 | PGND reference test point for input voltage |
VOUT_S | TP2 | Output voltage test point near output inductor |
PGND_S | TP19 | PGND reference test point for output voltage |