SLVUD40 November 2024 TPS25984B
- 1
- TPS25984BEVM: Evaluation Module for TPS25984B eFuse
- Trademarks
- 1Introduction
- 2Description
- 3Schematic
- 4General Configurations
-
5Test Setup and Procedures
- 5.1 Hot Plug
- 5.2 Start-Up With Enable
- 5.3 Difference Between Current Limit and DVDT Based Start-Up Mechanisms
- 5.4 Power Up Into Short
- 5.5 Overvoltage Lockout
- 5.6 Transient Overload Performance
- 5.7 Overcurrent Event
- 5.8 Output Hot Short
- 5.9 Quick Output Discharge (QOD)
- 5.10 Thermal Performance of TPS25984BEVM
- 6EVAL Board Assembly Drawings and Layout Guidelines
- 7Bill of Materials (BOM)
6.1 PCB Drawings
Figure 6-1 and Figure 6-2 show the component placements of the EVM. A pictorial representation of the TPS25984BEVM PCB layers can be found in Figure 6-3 to Figure 6-10.
Figure 6-1 TPS25984BEVM Board: Top
Assembly
Figure 6-3 TPS25984BEVM Board: Top
Layer
Figure 6-5 TPS25984BEVM Board: Layer
2 (Power)
Figure 6-7 TPS25984BEVM Board: Layer
4 (Signal)
Figure 6-9 TPS25984BEVM Board: Layer
6 (Power)
Figure 6-2 TPS25984BEVM Board: Bottom
Assembly
Figure 6-4 TPS25984BEVM Board: Bottom
Layer
Figure 6-6 TPS25984BEVM Board: Layer
3 (Power)
Figure 6-8 TPS25984BEVM Board: Layer
5 (Signal)
Figure 6-10 TPS25984BEVM Board: Layer
7 (Power)Note:
Analog signal nets, such as IREF, IMON, and TEMP, must be routed away as much as possible from power nets, such as VIN, VOUT, and PGND.