SLYT857 August 2024 TPS1200-Q1 , TPS1211-Q1

3 Parallel precharge path

This approach is typically used in high-current parallel FET-based designs that need an additional gate driver to drive a precharge FET, as shown in Figure 4. You can use Equation 3 to select the precharge resistor (Rpre-ch) in the precharge path to limit the inrush current to a specific value:

Equation 3.

R_{p r e - c h} = \frac{V_{I N}}{I_{I N R}}

Because the precharge resistor handles all of the power stress during startup, it should be able to handle both average and peak power dissipation, expressed by Equation 4 and Equation 5:

Equation 4.

P_{a v g} = \frac{E_{p r e - c h}}{T_{p r e - c h}} = \frac{0.5 \times C_{O U T} \times V_{I N}^{2}}{5 \times R_{p r e - c h} \times C_{O U T}}

Equation 5.

P_{p e a k} = \frac{V_{I N}^{2}}{R_{p r e - c h}}

Figure 4 Circuit with a precharge resistor and FET in a parallel path.

In this case, fast output charging is possible – at the cost of a very bulky precharge resistor. For example, charging 5mF to 12V in 10ms would require a 0.4Ω precharge resistor at a 36W rating with a peak power-handling capacity of 360W, resulting in a bulky wire-wound resistor. Thus, this solution is not viable for many types of end equipment, as there are many channels on the same PCB. Each channel would need a bulky resistor, resulting in a space-inefficient solution.